From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oo1-xc2e.google.com (mail-oo1-xc2e.google.com [IPv6:2607:f8b0:4864:20::c2e]) by sourceware.org (Postfix) with ESMTPS id 56DA33858D28 for ; Mon, 12 Jun 2023 03:32:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 56DA33858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oo1-xc2e.google.com with SMTP id 006d021491bc7-559409cc490so2557091eaf.3 for ; Sun, 11 Jun 2023 20:32:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686540728; x=1689132728; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=G2z934UIWDFJQ9cQvZlABXLGnhDYJ95/MoyICfB962g=; b=MCIxUbW4on9pImVoBkmt0KgOjjuvNCwJQsUwgElarizskIDZ58I/b8rUZLtswUvQQF LjN+MGJ0NNi8+GTyWjJr21iu7wvjRs5ote5A3qvfIGbz5qq/+tFkgmCEfkayskI5BYbg foeQ35QOAVxKt4vOmfyXaoAVo8yOBJeJ6/3ou+R2tUrEuFirKm/Uo/K0EMwedD/4HzKX jmhjNSVGdMr6VJd0DAcU65JJOlKkq0twyRjk82sHIpr1WDgh1jdgxvUlBtyAeQqrAxxf mdm24rxQ3Cu1AW8GrnwR43uqfbEb+w0cRsjDpwriprLng2XQ30RDHzBl9PmaWcxGz5+B qCmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686540728; x=1689132728; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=G2z934UIWDFJQ9cQvZlABXLGnhDYJ95/MoyICfB962g=; b=gwoID7ntOmz8eFeQetnwIA41EQYfzxI6OSeQc/1opghdSHe4HpWp9RfhosvIs3vABu VzWLEVu0KtTNI7Ff6bpbresUfr67xfkvhcPIrN386ATdULdmEuDJGT+MxeurvaUYhuWo xH+fWs68pfoQpBpXml5gvm6s84goUG8PCtcQYLy6nTKIs/GQi13YJLEwNzAUaRkDdeVt O9ELEmaaOU/CGULe9l4Z36iV0xaXzvhWgnEP/xZhGYSfEZMTFJyzhJxhvA+QstohFkau YlnYboLup6jd5sH6EMXOfDoaMDqmdYiEzcALJqImmTG5TG1hS45MuALkLK+xyvop0PRX ZmaA== X-Gm-Message-State: AC+VfDyER8OH22+vjyvzh4bEkwSjSNYKmDrF6y70eLpj3xvoJmXUEk7N ck68T/hf4ERPchDEKobrsNBIjwaJ6kjTwGGJod0= X-Google-Smtp-Source: ACHHUZ4U8gPlvEUTktKCO6rwvUGOy/bUpLo8wCQy6eXlvlpb9xCh7VD+sKgq6ijJ5vYXzt/Zthc7fZs2WNpnc6eONMk= X-Received: by 2002:a05:6358:cb14:b0:12b:e105:ec28 with SMTP id gr20-20020a056358cb1400b0012be105ec28mr475565rwb.21.1686540728230; Sun, 11 Jun 2023 20:32:08 -0700 (PDT) MIME-Version: 1.0 References: <20230612025721.3288649-1-pan2.li@intel.com> <537B258ED572FFB6+202306121057532717900@rivai.ai> In-Reply-To: <537B258ED572FFB6+202306121057532717900@rivai.ai> From: Kito Cheng Date: Mon, 12 Jun 2023 11:31:56 +0800 Message-ID: Subject: Re: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: "pan2.li" , gcc-patches , Robin Dapp , jeffreyalaw , "yanzhang.wang" Content-Type: multipart/alternative; boundary="000000000000016a4f05fde65d46" X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000016a4f05fde65d46 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LGTM juzhe.zhong@rivai.ai =E6=96=BC 2023=E5=B9=B46=E6=9C= =8812=E6=97=A5 =E9=80=B1=E4=B8=80 10:58 =E5=AF=AB=E9=81=93=EF=BC=9A > LGTM. > > > > juzhe.zhong@rivai.ai > > From: pan2.li > Date: 2023-06-12 10:57 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; > kito.cheng > Subject: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and > vlmul trunc > From: Pan Li > > This patch would like to add more tests for RVV FP16 undef and vlmul > trunc, aka > > __riscv_vundefined_f16*(); > __riscv_vlmul_trunc_v_f16*_f16*(); > > From the user's perspective, it is reasonable to do above operation > when only ZVFHMIN is enabled. This patch would like to add new test > cases to make sure the RVV FP16 vreinterpret works well as expected. > > Signed-off-by: Pan Li > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add test cases. > * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Ditto. > --- > .../riscv/rvv/base/zvfh-over-zvfhmin.c | 28 ++++++-- > .../riscv/rvv/base/zvfhmin-intrinsic.c | 66 +++++++++++++++---- > 2 files changed, 78 insertions(+), 16 deletions(-) > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c > index ff9e0156a68..c3ed4191a36 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c > @@ -45,15 +45,33 @@ vfloat16m8_t > test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t op1) { > return __riscv_vlmul_ext_v_f16mf4_f16m8(op1); > } > +vfloat16mf4_t test_vlmul_trunc_v_f16mf2_f16mf4(vfloat16mf2_t op1) { > + return __riscv_vlmul_trunc_v_f16mf2_f16mf4(op1); > +} > + > +vfloat16m4_t test_vlmul_trunc_v_f16m8_f16m4(vfloat16m8_t op1) { > + return __riscv_vlmul_trunc_v_f16m8_f16m4(op1); > +} > + > +vfloat16mf4_t test_vundefined_f16mf4() { > + return __riscv_vundefined_f16mf4(); > +} > + > +vfloat16m8_t test_vundefined_f16m8() { > + return __riscv_vundefined_f16m8(); > +} > + > /* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ > -/* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 6 } } */ > -/* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 8 } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ > /* { dg-final { scan-assembler-times > {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ > /* { dg-final { scan-assembler-times > {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */ > -/* { dg-final { scan-assembler-times > {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 6 } } */ > -/* { dg-final { scan-assembler-times > {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */ > +/* { dg-final { scan-assembler-times > {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 7 } } */ > +/* { dg-final { scan-assembler-times > {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */ > +/* { dg-final { scan-assembler-times > {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */ > /* { dg-final { scan-assembler-times > {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */ > -/* { dg-final { scan-assembler-times > {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */ > +/* { dg-final { scan-assembler-times > {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */ > +/* { dg-final { scan-assembler-times > {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > index 68720e64926..8d39a2ed4c2 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > @@ -121,26 +121,70 @@ vfloat16m8_t > test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t op1) { > return __riscv_vlmul_ext_v_f16mf4_f16m8(op1); > } > +vfloat16mf4_t test_vlmul_trunc_v_f16mf2_f16mf4(vfloat16mf2_t op1) { > + return __riscv_vlmul_trunc_v_f16mf2_f16mf4(op1); > +} > + > +vfloat16mf4_t test_vlmul_trunc_v_f16m1_f16mf4(vfloat16m1_t op1) { > + return __riscv_vlmul_trunc_v_f16m1_f16mf4(op1); > +} > + > +vfloat16mf2_t test_vlmul_trunc_v_f16m1_f16mf2(vfloat16m1_t op1) { > + return __riscv_vlmul_trunc_v_f16m1_f16mf2(op1); > +} > + > +vfloat16mf4_t test_vlmul_trunc_v_f16m2_f16mf4(vfloat16m2_t op1) { > + return __riscv_vlmul_trunc_v_f16m2_f16mf4(op1); > +} > + > +vfloat16m1_t test_vlmul_trunc_v_f16m2_f16m1(vfloat16m2_t op1) { > + return __riscv_vlmul_trunc_v_f16m2_f16m1(op1); > +} > + > +vfloat16mf4_t test_vlmul_trunc_v_f16m4_f16mf4(vfloat16m4_t op1) { > + return __riscv_vlmul_trunc_v_f16m4_f16mf4(op1); > +} > + > +vfloat16m2_t test_vlmul_trunc_v_f16m4_f16m2(vfloat16m4_t op1) { > + return __riscv_vlmul_trunc_v_f16m4_f16m2(op1); > +} > + > +vfloat16mf4_t test_vlmul_trunc_v_f16m8_f16mf4(vfloat16m8_t op1) { > + return __riscv_vlmul_trunc_v_f16m8_f16mf4(op1); > +} > + > +vfloat16m4_t test_vlmul_trunc_v_f16m8_f16m4(vfloat16m8_t op1) { > + return __riscv_vlmul_trunc_v_f16m8_f16m4(op1); > +} > + > +vfloat16mf4_t test_vundefined_f16mf4() { > + return __riscv_vundefined_f16mf4(); > +} > + > +vfloat16m8_t test_vundefined_f16m8() { > + return __riscv_vundefined_f16m8(); > +} > + > /* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ > -/* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 12 } } */ > -/* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 18 } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 6 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 } } */ > /* { dg-final { scan-assembler-times > {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 5 } } */ > /* { dg-final { scan-assembler-times > {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */ > /* { dg-final { scan-assembler-times > {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */ > -/* { dg-final { scan-assembler-times > {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */ > -/* { dg-final { scan-assembler-times > {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */ > -/* { dg-final { scan-assembler-times > {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */ > -/* { dg-final { scan-assembler-times > {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */ > +/* { dg-final { scan-assembler-times > {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */ > +/* { dg-final { scan-assembler-times > {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */ > +/* { dg-final { scan-assembler-times > {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ > +/* { dg-final { scan-assembler-times > {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ > /* { dg-final { scan-assembler-times > {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */ > -/* { dg-final { scan-assembler-times > {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */ > -/* { dg-final { scan-assembler-times > {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ > -/* { dg-final { scan-assembler-times > {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ > -/* { dg-final { scan-assembler-times > {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ > -/* { dg-final { scan-assembler-times > {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 11 } } */ > +/* { dg-final { scan-assembler-times > {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ > +/* { dg-final { scan-assembler-times > {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */ > +/* { dg-final { scan-assembler-times > {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */ > +/* { dg-final { scan-assembler-times > {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */ > +/* { dg-final { scan-assembler-times > {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ > -- > 2.34.1 > > > --000000000000016a4f05fde65d46--