From: Kito Cheng <kito.cheng@gmail.com>
To: pan2.li@intel.com
Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai,
kito.cheng@sifive.com, yanzhang.wang@intel.com
Subject: Re: [PATCH v2] RISC-V: Support RVV VREINTERPRET from vbool*_t to vint*m1_t
Date: Wed, 24 May 2023 11:22:18 +0800 [thread overview]
Message-ID: <CA+yXCZCuJ+D5oJoBn4RYqxxyZ-AJ5tjy7O6hdm6b+Ud_KZOP8Q@mail.gmail.com> (raw)
In-Reply-To: <20230518063652.3273735-1-pan2.li@intel.com>
LGTM
On Thu, May 18, 2023 at 2:37 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch support the RVV VREINTERPRET from the vbool*_t to the
> vint*m1_t. Aka:
>
> vint*m1_t __riscv_vreinterpret_x_x(vbool*_t);
>
> These APIs help the users to convert vector the vbool*_t to the LMUL=1
> signed integer vint*_t. According to the RVV intrinsic SPEC as below,
> the reinterpret intrinsics only change the types of the underlying contents.
>
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#reinterpret-vbool-o-vintm1
>
> For example, given below code.
> vint8m1_t test_vreinterpret_v_b1_vint8m1 (vbool1_t src) {
> return __riscv_vreinterpret_v_b1_i8m1 (src);
> }
>
> It will generate the assembly code similar as below:
> vsetvli a5,zero,e8,m8,ta,ma
> vlm.v v1,0(a1)
> vs1r.v v1,0(a0)
> ret
>
> Please NOTE the test files doesn't cover all the possible combinations
> of the intrinsic APIs introduced by this PATCH due to too many.
> The reinterpret from vbool*_t to vuint*m1_t with lmul=1 will be coverred
> in another PATCH.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/genrvv-type-indexer.cc (EEW_SIZE_LIST): New macro
> for the eew size list.
> (LMUL1_LOG2): New macro for the log2 value of lmul=1.
> (main): Add signed_eew*_lmul1_interpret for indexer.
> * config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
> Register vint*m1_t interpret function.
> * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
> New macro for vint8m1_t.
> (DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
> (DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
> (DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
> (vbool1_t): Add to signed_eew*_interpret_ops.
> (vbool2_t): Likewise.
> (vbool4_t): Likewise.
> (vbool8_t): Likewise.
> (vbool16_t): Likewise.
> (vbool32_t): Likewise.
> (vbool64_t): Likewise.
> * config/riscv/riscv-vector-builtins.cc (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
> New macro for vint*m1_t.
> (DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
> (DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
> (DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
> (required_extensions_p): Add vint8m1_t interpret case.
> * config/riscv/riscv-vector-builtins.def (signed_eew8_lmul1_interpret):
> Add vint*m1_t interpret to base type.
> (signed_eew16_lmul1_interpret): Likewise.
> (signed_eew32_lmul1_interpret): Likewise.
> (signed_eew64_lmul1_interpret): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c:
> Enrich the test cases.
> ---
> gcc/config/riscv/genrvv-type-indexer.cc | 13 ++++
> .../riscv/riscv-vector-builtins-functions.def | 4 ++
> .../riscv/riscv-vector-builtins-types.def | 64 +++++++++++++++++
> gcc/config/riscv/riscv-vector-builtins.cc | 70 +++++++++++++++++++
> gcc/config/riscv/riscv-vector-builtins.def | 6 ++
> .../rvv/base/misc_vreinterpret_vbool_vint.c | 19 ++++-
> 6 files changed, 175 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc
> index 33738e41d7c..5148abdda0f 100644
> --- a/gcc/config/riscv/genrvv-type-indexer.cc
> +++ b/gcc/config/riscv/genrvv-type-indexer.cc
> @@ -24,6 +24,8 @@ along with GCC; see the file COPYING3. If not see
> #include <math.h>
>
> #define BOOL_SIZE_LIST {1, 2, 4, 8, 16, 32, 64}
> +#define EEW_SIZE_LIST {8, 16, 32, 64}
> +#define LMUL1_LOG2 0
>
> std::string
> to_lmul (int lmul_log2)
> @@ -223,6 +225,10 @@ main (int argc, const char **argv)
> for (unsigned boolsize : BOOL_SIZE_LIST)
> fprintf (fp, " /*BOOL%d_INTERPRET*/ INVALID,\n", boolsize);
>
> + for (unsigned eew : EEW_SIZE_LIST)
> + fprintf (fp, " /*SIGNED_EEW%d_LMUL1_INTERPRET*/ %s,\n", eew,
> + inttype (eew, LMUL1_LOG2, /* unsigned_p */false).c_str ());
> +
> for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
> {
> unsigned multiple_of_lmul = 1 << lmul_log2_offset;
> @@ -312,6 +318,10 @@ main (int argc, const char **argv)
> : "INVALID");
> }
>
> + for (unsigned eew : EEW_SIZE_LIST)
> + fprintf (fp, " /*SIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n",
> + eew);
> +
> for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
> {
> unsigned multiple_of_lmul = 1 << lmul_log2_offset;
> @@ -374,6 +384,9 @@ main (int argc, const char **argv)
> for (unsigned boolsize : BOOL_SIZE_LIST)
> fprintf (fp, " /*BOOL%d_INTERPRET*/ INVALID,\n", boolsize);
>
> + for (unsigned eew : EEW_SIZE_LIST)
> + fprintf (fp, " /*SIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n", eew);
> +
> for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
> {
> unsigned multiple_of_lmul = 1 << lmul_log2_offset;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 7c89a20cb24..98d59294aae 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -515,6 +515,10 @@ DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool8_interpret_ops)
> DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool16_interpret_ops)
> DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool32_interpret_ops)
> DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool64_interpret_ops)
> +DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, b_v_signed_eew8_lmul1_interpret_ops)
> +DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, b_v_signed_eew16_lmul1_interpret_ops)
> +DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, b_v_signed_eew32_lmul1_interpret_ops)
> +DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, b_v_signed_eew64_lmul1_interpret_ops)
> DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x2_ops)
> DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x4_ops)
> DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x8_ops)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 5d1e5164b60..7b917094851 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -223,6 +223,34 @@ along with GCC; see the file COPYING3. If not see
> #define DEF_RVV_BOOL64_INTERPRET_OPS(TYPE, REQUIRE)
> #endif
>
> +/* Use "DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS" macro include all types for
> + INT8M1 vinterpret which will be iterated and registered as intrinsic
> + functions. */
> +#ifndef DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS
> +#define DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
> +#endif
> +
> +/* Use "DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS" macro include all types for
> + INT16M1 vinterpret which will be iterated and registered as intrinsic
> + functions. */
> +#ifndef DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS
> +#define DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
> +#endif
> +
> +/* Use "DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS" macro include all types for
> + INT32M1 vinterpret which will be iterated and registered as intrinsic
> + functions. */
> +#ifndef DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS
> +#define DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
> +#endif
> +
> +/* Use "DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS" macro include all types for
> + INT64M1 vinterpret which will be iterated and registered as intrinsic
> + functions. */
> +#ifndef DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS
> +#define DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
> +#endif
> +
> /* Use "DEF_RVV_X2_VLMUL_EXT_OPS" macro include all types for X2 VLMUL EXT
> which will be iterated and registered as intrinsic functions. */
> #ifndef DEF_RVV_X2_VLMUL_EXT_OPS
> @@ -770,6 +798,38 @@ DEF_RVV_BOOL64_INTERPRET_OPS (vuint16m1_t, 0)
> DEF_RVV_BOOL64_INTERPRET_OPS (vuint32m1_t, 0)
> DEF_RVV_BOOL64_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
>
> +DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool1_t, 0)
> +DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool2_t, 0)
> +DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool4_t, 0)
> +DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool8_t, 0)
> +DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool16_t, 0)
> +DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool32_t, 0)
> +DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
> +
> +DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool1_t, 0)
> +DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool2_t, 0)
> +DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool4_t, 0)
> +DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool8_t, 0)
> +DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool16_t, 0)
> +DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool32_t, 0)
> +DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
> +
> +DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool1_t, 0)
> +DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool2_t, 0)
> +DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool4_t, 0)
> +DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool8_t, 0)
> +DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool16_t, 0)
> +DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool32_t, 0)
> +DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
> +
> +DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool1_t, 0)
> +DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool2_t, 0)
> +DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool4_t, 0)
> +DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool8_t, 0)
> +DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool16_t, 0)
> +DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool32_t, 0)
> +DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool64_t, RVV_REQUIRE_ELEN_64)
> +
> DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf4_t, 0)
> DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf2_t, 0)
> @@ -1164,6 +1224,10 @@ DEF_RVV_TUPLE_OPS (vfloat64m4x2_t, RVV_REQUIRE_ELEN_FP_64)
> #undef DEF_RVV_BOOL16_INTERPRET_OPS
> #undef DEF_RVV_BOOL32_INTERPRET_OPS
> #undef DEF_RVV_BOOL64_INTERPRET_OPS
> +#undef DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS
> +#undef DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS
> +#undef DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS
> +#undef DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS
> #undef DEF_RVV_X2_VLMUL_EXT_OPS
> #undef DEF_RVV_X4_VLMUL_EXT_OPS
> #undef DEF_RVV_X8_VLMUL_EXT_OPS
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index 859bd1c35ab..1614483c06c 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -373,6 +373,34 @@ static const rvv_type_info bool64_interpret_ops[] = {
> #include "riscv-vector-builtins-types.def"
> {NUM_VECTOR_TYPES, 0}};
>
> +/* A list of vint8m1 interpret will be registered for intrinsic functions. */
> +static const rvv_type_info signed_eew8_lmul1_interpret_ops[] = {
> +#define DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS(TYPE, REQUIRE) \
> + {VECTOR_TYPE_##TYPE, REQUIRE},
> +#include "riscv-vector-builtins-types.def"
> + {NUM_VECTOR_TYPES, 0}};
> +
> +/* A list of vint16m1 interpret will be registered for intrinsic functions. */
> +static const rvv_type_info signed_eew16_lmul1_interpret_ops[] = {
> +#define DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS(TYPE, REQUIRE) \
> + {VECTOR_TYPE_##TYPE, REQUIRE},
> +#include "riscv-vector-builtins-types.def"
> + {NUM_VECTOR_TYPES, 0}};
> +
> +/* A list of vint32m1 interpret will be registered for intrinsic functions. */
> +static const rvv_type_info signed_eew32_lmul1_interpret_ops[] = {
> +#define DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS(TYPE, REQUIRE) \
> + {VECTOR_TYPE_##TYPE, REQUIRE},
> +#include "riscv-vector-builtins-types.def"
> + {NUM_VECTOR_TYPES, 0}};
> +
> +/* A list of vint64m1 interpret will be registered for intrinsic functions. */
> +static const rvv_type_info signed_eew64_lmul1_interpret_ops[] = {
> +#define DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(TYPE, REQUIRE) \
> + {VECTOR_TYPE_##TYPE, REQUIRE},
> +#include "riscv-vector-builtins-types.def"
> + {NUM_VECTOR_TYPES, 0}};
> +
> /* A list of x2 vlmul ext will be registered for intrinsic functions. */
> static const rvv_type_info vlmul_ext_x2_ops[] = {
> #define DEF_RVV_X2_VLMUL_EXT_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
> @@ -1701,6 +1729,38 @@ static CONSTEXPR const rvv_op_info iu_v_bool64_interpret_ops
> rvv_arg_type_info (RVV_BASE_bool64_interpret), /* Return type */
> v_args /* Args */};
>
> +/* A static operand information for vint8_t func (vector_type)
> + * function registration. */
> +static CONSTEXPR const rvv_op_info b_v_signed_eew8_lmul1_interpret_ops
> + = {signed_eew8_lmul1_interpret_ops, /* Types */
> + OP_TYPE_v, /* Suffix */
> + rvv_arg_type_info (RVV_BASE_signed_eew8_lmul1_interpret),/* Return type */
> + v_args /* Args */};
> +
> +/* A static operand information for vint16_t func (vector_type)
> + * function registration. */
> +static CONSTEXPR const rvv_op_info b_v_signed_eew16_lmul1_interpret_ops
> + = {signed_eew16_lmul1_interpret_ops, /* Types */
> + OP_TYPE_v, /* Suffix */
> + rvv_arg_type_info (RVV_BASE_signed_eew16_lmul1_interpret),/* Return type */
> + v_args /* Args */};
> +
> +/* A static operand information for vint32_t func (vector_type)
> + * function registration. */
> +static CONSTEXPR const rvv_op_info b_v_signed_eew32_lmul1_interpret_ops
> + = {signed_eew32_lmul1_interpret_ops, /* Types */
> + OP_TYPE_v, /* Suffix */
> + rvv_arg_type_info (RVV_BASE_signed_eew32_lmul1_interpret),/* Return type */
> + v_args /* Args */};
> +
> +/* A static operand information for vint64_t func (vector_type)
> + * function registration. */
> +static CONSTEXPR const rvv_op_info b_v_signed_eew64_lmul1_interpret_ops
> + = {signed_eew64_lmul1_interpret_ops, /* Types */
> + OP_TYPE_v, /* Suffix */
> + rvv_arg_type_info (RVV_BASE_signed_eew64_lmul1_interpret),/* Return type */
> + v_args /* Args */};
> +
> /* A static operand information for vector_type func (vector_type)
> * function registration. */
> static CONSTEXPR const rvv_op_info all_v_vlmul_ext_x2_ops
> @@ -2389,6 +2449,8 @@ static CONSTEXPR const function_type_info function_types[] = {
> EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, \
> BOOL1_INTERPRET, BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, \
> BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET, \
> + SIGNED_EEW8_LMUL1_INTERPRET, SIGNED_EEW16_LMUL1_INTERPRET, \
> + SIGNED_EEW32_LMUL1_INTERPRET, SIGNED_EEW64_LMUL1_INTERPRET, \
> X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT, \
> X64_VLMUL_EXT, TUPLE_SUBPART) \
> { \
> @@ -2433,6 +2495,10 @@ static CONSTEXPR const function_type_info function_types[] = {
> VECTOR_TYPE_##BOOL16_INTERPRET, \
> VECTOR_TYPE_##BOOL32_INTERPRET, \
> VECTOR_TYPE_##BOOL64_INTERPRET, \
> + VECTOR_TYPE_##SIGNED_EEW8_LMUL1_INTERPRET, \
> + VECTOR_TYPE_##SIGNED_EEW16_LMUL1_INTERPRET, \
> + VECTOR_TYPE_##SIGNED_EEW32_LMUL1_INTERPRET, \
> + VECTOR_TYPE_##SIGNED_EEW64_LMUL1_INTERPRET, \
> VECTOR_TYPE_##X2_VLMUL_EXT, \
> VECTOR_TYPE_##X4_VLMUL_EXT, \
> VECTOR_TYPE_##X8_VLMUL_EXT, \
> @@ -2741,6 +2807,10 @@ required_extensions_p (enum rvv_base_type type)
> case RVV_BASE_bool16_interpret:
> case RVV_BASE_bool32_interpret:
> case RVV_BASE_bool64_interpret:
> + case RVV_BASE_signed_eew8_lmul1_interpret:
> + case RVV_BASE_signed_eew16_lmul1_interpret:
> + case RVV_BASE_signed_eew32_lmul1_interpret:
> + case RVV_BASE_signed_eew64_lmul1_interpret:
> case RVV_BASE_vlmul_ext_x2:
> case RVV_BASE_vlmul_ext_x4:
> case RVV_BASE_vlmul_ext_x8:
> diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
> index cb409a8cab7..9137a364f6e 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -81,6 +81,8 @@ along with GCC; see the file COPYING3. If not see
> EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, \
> BOOL1_INTERPRET, BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, \
> BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET, \
> + SIGNED_EEW8_LMUL1_INTERPRET, SIGNED_EEW16_LMUL1_INTERPRET, \
> + SIGNED_EEW32_LMUL1_INTERPRET, SIGNED_EEW64_LMUL1_INTERPRET, \
> X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT, \
> X64_VLMUL_EXT, TUPLE_SUBPART)
> #endif
> @@ -643,6 +645,10 @@ DEF_RVV_BASE_TYPE (bool8_interpret, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (bool16_interpret, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (bool32_interpret, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (bool64_interpret, get_vector_type (type_idx))
> +DEF_RVV_BASE_TYPE (signed_eew8_lmul1_interpret, get_vector_type (type_idx))
> +DEF_RVV_BASE_TYPE (signed_eew16_lmul1_interpret, get_vector_type (type_idx))
> +DEF_RVV_BASE_TYPE (signed_eew32_lmul1_interpret, get_vector_type (type_idx))
> +DEF_RVV_BASE_TYPE (signed_eew64_lmul1_interpret, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (vlmul_ext_x2, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (vlmul_ext_x4, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (vlmul_ext_x8, get_vector_type (type_idx))
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
> index d4cf9d4a07e..9b03726b63a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
> @@ -82,5 +82,22 @@ vbool64_t test_vreinterpret_v_u8m1_b64 (vuint8m1_t src) {
> return __riscv_vreinterpret_v_u8m1_b64 (src);
> }
>
> -/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
> +vint8m1_t test_vreinterpret_v_b1_vint8m1 (vbool1_t src) {
> + return __riscv_vreinterpret_v_b1_i8m1 (src);
> +}
> +
> +vint16m1_t test_vreinterpret_v_b1_vint16m1 (vbool1_t src) {
> + return __riscv_vreinterpret_v_b1_i16m1 (src);
> +}
> +
> +vint32m1_t test_vreinterpret_v_b1_vint32m1 (vbool1_t src) {
> + return __riscv_vreinterpret_v_b1_i32m1 (src);
> +}
> +
> +vint64m1_t test_vreinterpret_v_b1_vint64m1 (vbool1_t src) {
> + return __riscv_vreinterpret_v_b1_i64m1 (src);
> +}
> +
> +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 24 } } */
> /* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
> +/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-05-24 3:22 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <Message-Id: <20230518031725.3164716-1-pan2.li@intel.com>
2023-05-18 6:36 ` pan2.li
2023-05-24 3:22 ` Kito Cheng [this message]
2023-05-24 3:30 ` Li, Pan2
2023-05-18 3:17 [PATCH] " pan2.li
2023-05-18 6:40 ` Li, Pan2
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