From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by sourceware.org (Postfix) with ESMTPS id DA9A03858CD1 for ; Mon, 8 Jan 2024 03:06:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DA9A03858CD1 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DA9A03858CD1 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::332 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704683198; cv=none; b=hghv6lMqW2P0lvS4zpR2VErD2QsdZTBMAqZzwtIgKtov/0YodyXiwKKr+hLIjY3VXi+sPakHY0zoSorkWvfHgWFh3l0AlCnhScTgrdpdx/IYk3cRWe9h6TTxivoTOP3nYshcCvHxHXSqMXmBF7r968gUPmkshQQYSI8xNn8C7ZA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704683198; c=relaxed/simple; bh=W0AqT861KAah2sQYdquqGiR/Dy7cB4klEIDHDjm2NGA=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=OmJpiGH6oXJf/55fVYX/VoVDfFyQPnL515p4fnQoakqiIGPGHR9wI0StSWKuEdW540DHxdMEE6+AhmIrvk1kjcwnInHeHHEneqAvsZ5853UeOG30FZwUI64zjA+3JMatBgQJ5NXukW4T/1E4u3ayppErjzjwa3pAbgjYaVa9GIs= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40d8e7a50c1so18886095e9.2 for ; Sun, 07 Jan 2024 19:06:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704683194; x=1705287994; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=jGJb/JuEwLaLgSXU2pXDNcPWYcQi1Ext4Up4FGTdPWo=; b=MOoxjHBMHKpMYk9Cjh51eUvvYENhGjC19WjmSzkenDE3/pwWbNOg/dgsWzIlUR/F7d PDW2FwkkNxL1Q8PWWetaqr1OeujKH69Khf81ymPSFfDg1QwMsiOG3d0TTRgUiu9CQ1q4 7jW0dZvJoHDKv1UXyPBnNTF3PCV+usgXjAKY9027fSqhzb54A6IGDogXv8swQTb4CHom 7XP420zxhtFX5zeqSV3bmc0mMm7gtXdVtg82wqAYHPOc6ujxNbFmA+nGKWP9erqoiLLC 1H0lfSEh2U1D4tim9MgwiV8rKD3AGiAQlroc8fmyNpKXLV2bZAJh6oxX+4tKHT/CGgNc lwXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704683194; x=1705287994; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jGJb/JuEwLaLgSXU2pXDNcPWYcQi1Ext4Up4FGTdPWo=; b=U7IvCR6mDhQatSjKxkmrQICICXOQILfmNGcpRRUt4iWJTkURYUruQ5IRZNd8xI8qaW c0Us9+NAUaKWPIZDimif853E4xRxs+pFkr+pLKJkzjTdIXzjzN9aURp/Q4HF/nn42ZBO gefrBidvdMGbM0tWVYMmE/neeV96nCtgKi8pGKb5IU46chrwggn4AZNOqrkgBn/3MsVN YKbqpVZostI2HVIwY3GShO6AZ65eG7usPTch7+lWp94ex/Zep0U2GmD/r/ZcdbNO2ZmG bHatiwrD1qZ9KzhvnVxAmgqmgaQURVAUc6U8WtJlAz+WLNhL3cSPYcP/FL+MkcXz72oN Fi8A== X-Gm-Message-State: AOJu0YxBNUYw+objsnIdL2KiyJH9hf8DU2XpIxlAPeMvVJLWW4KAaUvE 26KtAhiWDP1PD+ilPzZmzo7ds+yxFIhPf4WzRuM= X-Google-Smtp-Source: AGHT+IFwOVxLz9IrgOlBPWGYsrrb6EYcSsNgzSJPjl3mGZ9Cz802jsrgmkgAfM7sEjs7SjoWrw8xwn++p64lughoy1o= X-Received: by 2002:a05:600c:3507:b0:40d:8dcc:ffd6 with SMTP id h7-20020a05600c350700b0040d8dccffd6mr1516406wmq.136.1704683194349; Sun, 07 Jan 2024 19:06:34 -0800 (PST) MIME-Version: 1.0 References: <9C9A2CEFF50F1A0D+2024010417182466760410@rivai.ai> <69319640-71b3-4167-9ca7-0f0362307199.cooper.joshua@linux.alibaba.com> In-Reply-To: <69319640-71b3-4167-9ca7-0f0362307199.cooper.joshua@linux.alibaba.com> From: Kito Cheng Date: Mon, 8 Jan 2024 11:06:22 +0800 Message-ID: Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. To: joshua Cc: "juzhe.zhong@rivai.ai" , jeffreyalaw , gcc-patches , Jim Wilson , palmer , andrew , "philipp.tomsich" , "christoph.muellner" , jinma , "cooper.qu" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: I am ok with merging this for GCC 14, as we discussed several times in the RISC-V GCC sync up meeting, I think at least we reach consensus among Jeff Law, Palmer Dabbelt and me. But please be careful: don't break anything for standard vector stuff. On Mon, Jan 8, 2024 at 10:11=E2=80=AFAM joshua wrote: > > Hi Juzhe, > > Stage 3 will close today and there are still some patches that > haven't been reviewed left. > So is it possible to get xtheadvector merged in GCC-14? > We emailed Kito regarding this, but haven't got any reply yet. > > Joshua > > > > > > > ------------------------------------------------------------------ > =E5=8F=91=E4=BB=B6=E4=BA=BA=EF=BC=9Ajuzhe.zhong@rivai.ai > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4=EF=BC=9A2024=E5=B9=B41=E6=9C=884=E6= =97=A5(=E6=98=9F=E6=9C=9F=E5=9B=9B) 17:18 > =E6=94=B6=E4=BB=B6=E4=BA=BA=EF=BC=9A"cooper.joshua"; jeffreyalaw; "gcc-patches" > =E6=8A=84=E3=80=80=E9=80=81=EF=BC=9AJim Wilson;= palmer; andrew; "philipp.tomsich"; "christoph.muellner"= ; jinma; "cooper.qu" > =E4=B8=BB=E3=80=80=E9=A2=98=EF=BC=9ARe: Re: [PATCH v4] RISC-V: Adds the p= refix "th." for the instructions of XTheadVector. > > > \ No newline at end of file > Each file needs newline. > > > I am not able to review arch stuff. This needs kito. > > > Besides, Andrew Pinski want us defer theadvector to GCC-15. > > > I have no strong opinion here. > > > juzhe.zhong@rivai.ai > > > =E5=8F=91=E4=BB=B6=E4=BA=BA=EF=BC=9A joshua > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4=EF=BC=9A 2024-01-04 17:15 > =E6=94=B6=E4=BB=B6=E4=BA=BA=EF=BC=9A =E9=92=9F=E5=B1=85=E5=93=B2; Jeff La= w; gcc-patches > =E6=8A=84=E9=80=81=EF=BC=9A jim.wilson.gcc; palmer; andrew; philipp.tomsi= ch; Christoph M=C3=BCllner; jinma; Cooper Qu > =E4=B8=BB=E9=A2=98=EF=BC=9A Re=EF=BC=9ARe: [PATCH v4] RISC-V: Adds the pr= efix "th." for the instructions of XTheadVector. > > Hi Juzhe, > > So is the following patch that this patch relies on OK to commit? > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html > > Joshua > > > > > ------------------------------------------------------------------ > =E5=8F=91=E4=BB=B6=E4=BA=BA=EF=BC=9A=E9=92=9F=E5=B1=85=E5=93=B2 > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4=EF=BC=9A2024=E5=B9=B41=E6=9C=882=E6= =97=A5(=E6=98=9F=E6=9C=9F=E4=BA=8C) 06:57 > =E6=94=B6=E4=BB=B6=E4=BA=BA=EF=BC=9AJeff Law; "coo= per.joshua"; "gcc-patches" > =E6=8A=84=E3=80=80=E9=80=81=EF=BC=9A"jim.wilson.gcc"; palmer; andrew; "philipp.toms= ich"; "Christoph M=C3=BCllner"; jinma; Cooper Qu > =E4=B8=BB=E3=80=80=E9=A2=98=EF=BC=9ARe: Re: [PATCH v4] RISC-V: Adds the p= refix "th." for the instructions of XTheadVector. > > > This is Ok from my side. > But before commit this patch, I think we need this patch first: > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html > > > I will be back to work so I will take a look at other patches today. > juzhe.zhong@rivai.ai > > > From: Jeff Law > Date: 2024-01-01 01:43 > To: Jun Sha (Joshua); gcc-patches > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; = juzhe.zhong; Jin Ma; Xianmiao Qu > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instruction= s of XTheadVector. > > > > On 12/28/23 21:19, Jun Sha (Joshua) wrote: > > This patch adds th. prefix to all XTheadVector instructions by > > implementing new assembly output functions. We only check the > > prefix is 'v', so that no extra attribute is needed. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode): > > New function to add assembler insn code prefix/suffix. > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise. > > > > Co-authored-by: Jin Ma > > Co-authored-by: Xianmiao Qu > > Co-authored-by: Christoph M=C3=BCllner > > --- > > gcc/config/riscv/riscv-protos.h | 1 + > > gcc/config/riscv/riscv.cc | 14 +++++++++++++= + > > gcc/config/riscv/riscv.h | 4 ++++ > > .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 ++++++++++++ > > 4 files changed, 31 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr= efix.c > > > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-p= rotos.h > > index 31049ef7523..5ea54b45703 100644 > > --- a/gcc/config/riscv/riscv-protos.h > > +++ b/gcc/config/riscv/riscv-protos.h > > @@ -102,6 +102,7 @@ struct riscv_address_info { > > }; > > > > /* Routines implemented in riscv.cc. */ > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const = char *p); > > extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx= ); > > extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *)= ; > > extern int riscv_float_const_rtx_index_for_fli (rtx); > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > index 0d1cbc5cb5f..ea1d59d9cf2 100644 > > --- a/gcc/config/riscv/riscv.cc > > +++ b/gcc/config/riscv/riscv.cc > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode) > > return lmul; > > } > > > > +/* Define ASM_OUTPUT_OPCODE to do anything special before > > + emitting an opcode. */ > > +const char * > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) > > +{ > > + /* We need to add th. prefix to all the xtheadvector > > + insturctions here.*/ > > + if (TARGET_XTHEADVECTOR && current_output_insn !=3D NULL_RTX && > > + p[0] =3D=3D 'v') > > + fputs ("th.", asm_out_file); > > + > > + return p; > Just a formatting nit. The GNU standards break lines before the > operator, not after. So > if (TARGET_XTHEADVECTOR > && current_output_insn !=3D NULL > && p[0] =3D=3D 'v') > > Note that current_output_insn is "extern rtx_insn *", so use NULL, not > NULL_RTX. > > Neither of these nits require a new version for review. Just fix them. > > If Juzhe is fine with this, so am I. We can refine it if necessary later= . > > jeff > > > > >