Re: RISC-V: Replace unspec with bitreverse in riscv_brev8_<mode> insn

[Kito Cheng <kito.cheng@gmail.com>]

My understanding is the semantic is slightly different, brev8 is only
the bit reverse within each byte, but bitreverse means did bit reverse
for the whole content of the mode, e.g. riscv_brev8_si will bit
reserved within 32 bit.

Using RV32 as example:
UNSPEC_BREV8:
rd[0...7]  = rs[7...0]
rd[8...15]  = rs[15...8]
rd[16...23]  = rs[23...16]
rd[16...23]  = rs[31...24]

bitreverse:
rd[0...31] = rs[31...0]

On Wed, Jul 26, 2023 at 3:55 PM Jivan Hakobyan via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> This small patch replaces unspec opcode with bitreverse in
> riscv_brev8_<mode> insn.
>
> gcc/ChangeLog:
>         * config/riscv/crypto.md (UNSPEC_BREV8): Remov.
>         (riscv_brev8_<mode>): Use bitreverse opcode.
>
>
> --
> With the best regards
> Jivan Hakobyan