From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 5E7323858C54 for ; Fri, 2 Sep 2022 10:08:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5E7323858C54 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x631.google.com with SMTP id se27so2836465ejb.8 for ; Fri, 02 Sep 2022 03:08:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=BOxBzvcmEhs/4hJoz90Y0UGGzLF7vHdwFDjPny3+6go=; b=LnGTDrRemMMk+ihF3jtdRDEIjLx/ntW82FZKWJ6CiFbGyb5XMMveOzLaN3eHupP/jR 12keA3Zqhh0bk6fsSnBD2tzj31WE1Ce0odfUHUSwaFHTTHwMyvntL+edFNjUI96FzdGo ZjJvlf2ggxzEsy2cYfBrQMaFk0cbOXKhYjoT3becbxemBMHd7vm2awFtkXVdcrn3sCwl ienD7da/s0aeO+DTkLSxegfIbzDIEpx1XUnFYLrePd8f12t+3Sudxcezm+jPwzTDGJI8 KK5MtMDAb8S1k8BBx5j0ylSNuQIcA4tSav0tJEHpaAZ6O7sPrMWH3qdE8fy6gLX38DJ3 025g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=BOxBzvcmEhs/4hJoz90Y0UGGzLF7vHdwFDjPny3+6go=; b=K1nigtOFU83U7P3a7ApNsVOzrQGElRd4MWju9YtO4LCNYYNltzU6tyyv1uQiOxRawp 9Yt3S4fkx5G8dXgwPr6R/hdw4tm8XO7Ra8JoLDpOVnNt9ozOjvYrPRNLuMBsg2TGAdJ7 SxvKHWIFx4CHqt0oxO3YHAot5CspRuULr2pVQppYXnHriPvXhD4OPpag5gM1vYT/ipSk Pjgajs8BZMeosrWx8ydhmThoYTcvlEDhi7gz/2/tqlsVkRA4UbEciyj+mA44aJq8sdQN x/EzMhriP1Ep1De0eMhRNw1TxxzbGVgjY8henK2U4XT+AjFGfyiMzsPkeImpHXAX1pT7 h47A== X-Gm-Message-State: ACgBeo2lv04SqFTwLI7sqYs2lZ+nJHES0HO3M0vEwbG+wEFieHqqUtJQ WMCMRNm/3SXJtDZ99RoIPmfHXG4DNu0TnnExvFY= X-Google-Smtp-Source: AA6agR7TU6xw38BdLJVLYb4/FYJeQ327O2efXqeK0YHCc7HtY0DTFnWP0PNadOjkH56Gl7Re65504egzC4pdA/A6rrk= X-Received: by 2002:a17:907:2e0d:b0:741:a3ec:7f92 with SMTP id ig13-20020a1709072e0d00b00741a3ec7f92mr14423548ejc.309.1662113296498; Fri, 02 Sep 2022 03:08:16 -0700 (PDT) MIME-Version: 1.0 References: <20220821215823.18207-1-palmer@rivosinc.com> In-Reply-To: <20220821215823.18207-1-palmer@rivosinc.com> From: Kito Cheng Date: Fri, 2 Sep 2022 18:08:04 +0800 Message-ID: Subject: Re: [PATCH v4] RISC-V: Add support for inlining subword atomic operations To: Palmer Dabbelt Cc: GCC Patches , "Patrick O'Neill" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM with minor comments, it's time to move forward, thanks Patrick and Palmer. > + > +void > +riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask, > + rtx *not_mask) > +{ > + /* Align the memory addess to a word. */ > + rtx addr = force_reg (Pmode, XEXP (mem, 0)); > + > + rtx aligned_addr = gen_reg_rtx (Pmode); > + emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, > + gen_int_mode (-4, Pmode))); > + > + *aligned_mem = change_address (mem, SImode, aligned_addr); > + > + /* Calculate the shift amount. */ > + *shift = gen_reg_rtx (SImode); Already allocated reg_rtx outside, this line could be removed. > + emit_move_insn (*shift, gen_rtx_AND (SImode, gen_lowpart (SImode, addr), > + gen_int_mode (3, SImode))); > + emit_move_insn (*shift, gen_rtx_ASHIFT (SImode, *shift, > + gen_int_mode(3, SImode))); > + > + /* Calculate the mask. */ > + int unshifted_mask; > + if (GET_MODE (mem) == QImode) > + unshifted_mask = 0xFF; > + else > + unshifted_mask = 0xFFFF; > + > + rtx mask_reg = gen_reg_rtx (SImode); Ditto. > @@ -152,6 +348,128 @@ > DONE; > }) > > +(define_expand "atomic_compare_and_swap" > + [(match_operand:SI 0 "register_operand" "") ;; bool output > + (match_operand:SHORT 1 "register_operand" "") ;; val output > + (match_operand:SHORT 2 "memory_operand" "") ;; memory > + (match_operand:SHORT 3 "reg_or_0_operand" "") ;; expected value > + (match_operand:SHORT 4 "reg_or_0_operand" "") ;; desired value > + (match_operand:SI 5 "const_int_operand" "") ;; is_weak > + (match_operand:SI 6 "const_int_operand" "") ;; mod_s > + (match_operand:SI 7 "const_int_operand" "")] ;; mod_f > + "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" > +{ > + emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], > + operands[3], operands[4], > + operands[6], operands[7])); > + > + rtx val = gen_reg_rtx (SImode); > + if (operands[1] != const0_rtx) > + emit_insn (gen_rtx_SET (val, gen_rtx_SIGN_EXTEND (SImode, operands[1]))); > + else > + emit_insn (gen_rtx_SET (val, const0_rtx)); nit: emit_move_insn rather than emit_insn + gen_rtx_SET > + > + rtx exp = gen_reg_rtx (SImode); > + if (operands[3] != const0_rtx) > + emit_insn (gen_rtx_SET (exp, gen_rtx_SIGN_EXTEND (SImode, operands[3]))); > + else > + emit_insn (gen_rtx_SET (exp, const0_rtx)); nit: emit_move_insn rather than emit_insn + gen_rtx_SET > + > + rtx compare = val; > + if (exp != const0_rtx) > + { > + rtx difference = gen_rtx_MINUS (SImode, val, exp); > + compare = gen_reg_rtx (SImode); > + emit_insn (gen_rtx_SET (compare, difference)); nit: emit_move_insn rather than emit_insn + gen_rtx_SET > + } > + > + if (word_mode != SImode) > + { > + rtx reg = gen_reg_rtx (word_mode); > + emit_insn (gen_rtx_SET (reg, gen_rtx_SIGN_EXTEND (word_mode, compare))); nit: emit_move_insn rather than emit_insn + gen_rtx_SET > + compare = reg; > + } > + > + emit_insn (gen_rtx_SET (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx))); nit: emit_move_insn rather than emit_insn + gen_rtx_SET