From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id BCD7C385F022 for ; Fri, 30 Sep 2022 15:23:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BCD7C385F022 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62c.google.com with SMTP id lh5so9700567ejb.10 for ; Fri, 30 Sep 2022 08:23:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=HMz/KYE+JvVAj8xpm3Bjnv9SBbkcs3aZmcEA4afSp1M=; b=doN9yLtafmmikJ+RemuNSvCLeCEMMtcnsigY8+1NQvFgdm8OgTDKMOV+Hq2sm8nd+r lV8IGpkiTqS7wBLswTlWUoadx03Q5jKf0/a/dXQz6LuL7F5HBXHKWSO3fSD4rVNF7T/b 9+qZtr0BikCrFSS/OKphFHiQlrJKtjVwD3PPKNIkUeoJqFHAFGa53UQ662xr4KEEg0ZW 4q/9WzH2+gYW5F/UdQgpjLeWb8JpyJKIMkLYTrrGGfN2NiaR9QLMjla/qvg9A1WWrFG1 Zdnxljz8ZbMmnFnYJFG5cBKzV6H/d1gZcsbu+64magSK/cQy+eZuYWVoZj6QVFK33mz3 wanA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=HMz/KYE+JvVAj8xpm3Bjnv9SBbkcs3aZmcEA4afSp1M=; b=z5q2+0Z/zRfh2ZWjQK1qSG00bja5h6R8bsXlChtED96L9iMnB1FDkwq36TXliB+PZA km7i0/SoQSml1lcUigN81Psnt3BhRsaw+scuH8Zq6Cg9bCAVNoZSaX6KvJfBXyWzUpoc pfPI4SVvoGJk5/tq59z9MxPY2S/4s7vk+VQURAXW3vECVfPfzWGRapt34nb8w+xnh8h7 mI3Y+gVW4blV+/an4K1xgk0/tihpSyPrUYCZEjkZ/OmNtaABM07G1alwmfSKnywNwimP 0k0B27LxZmMkKsxu895wSplX1EZ/O8CUJu4JhP8wHFDx///4aJ79KQfJ9bzLa1mWY9iK Xwug== X-Gm-Message-State: ACrzQf1dsogLMSuLgJbNRoo4SKfN9yz/IDVXEsyaSBCPBRspDGfweAmX i8wvwN60J1MMraULo4lrUYyas8aFAuSQ2egQZw0= X-Google-Smtp-Source: AMsMyM6TDrM4JlqnY0SPdGXLRMFqxbdnAu8Rsvglrecg9cmiNeL1UtzBOnfBscPoXIhNB3IYIHjHdgWMGbQIboQCqc4= X-Received: by 2002:a17:907:2e02:b0:77c:5020:b8ef with SMTP id ig2-20020a1709072e0200b0077c5020b8efmr6883703ejc.299.1664551406944; Fri, 30 Sep 2022 08:23:26 -0700 (PDT) MIME-Version: 1.0 References: <20220913093616.1422179-1-jiawei@iscas.ac.cn> In-Reply-To: <20220913093616.1422179-1-jiawei@iscas.ac.cn> From: Kito Cheng Date: Fri, 30 Sep 2022 23:23:14 +0800 Message-ID: Subject: Re: [V2 PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc. To: jiawei Cc: GCC Patches , wuwei2016@iscas.ac.cn, Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed, but I decided to take v1 and disable that by default to prevent breaking the existing code :) On Tue, Sep 13, 2022 at 5:37 PM jiawei wrote: > > From: Jiawei > > Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option, > it will add csr-check in .option section and pass this to assembler. > > V2: Add assembler support check info for -mcsr-check. Thanks for Kito's > suggestions. > > gcc/ChangeLog: > > * config.in: New def. > * config/riscv/riscv.cc (riscv_file_start): New .option. > * config/riscv/riscv.opt: New options. > * configure.ac: New check. > * doc/invoke.texi: New def. > > --- > gcc/config.in | 6 ++++++ > gcc/config/riscv/riscv.cc | 5 +++++ > gcc/config/riscv/riscv.opt | 6 ++++++ > gcc/configure.ac | 5 +++++ > gcc/doc/invoke.texi | 6 ++++++ > 5 files changed, 28 insertions(+) > > diff --git a/gcc/config.in b/gcc/config.in > index 9c53319b544..a4c39e1384d 100644 > --- a/gcc/config.in > +++ b/gcc/config.in > @@ -616,6 +616,12 @@ > #endif > > > +/* Define if your assembler supports -mcsr-check. */ > +#ifndef USED_FOR_TARGET > +#undef HAVE_AS_MCSR_CHECK > +#endif > + > + > /* Define if your Mac OS X assembler supports -mllvm -x86-pad-for-align=false. > */ > #ifndef USED_FOR_TARGET > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 675d92c0961..e98e6b1f561 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5135,6 +5135,11 @@ riscv_file_start (void) > if (! riscv_mrelax) > fprintf (asm_out_file, "\t.option norelax\n"); > > + /* If the user specifies "-mcsr-check" on the command line then enable csr > + check in the assembler. */ > + if (riscv_mcsr_check) > + fprintf (asm_out_file, "\t.option csr-check\n"); > + > if (riscv_emit_attribute_p) > riscv_emit_attribute (); > } > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index fbca91b956c..3a12dd47310 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1) > Take advantage of linker relaxations to reduce the number of instructions > required to materialize symbol addresses. > > +mcsr-check > +Target Bool Var(riscv_mcsr_check) Init(1) > +Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. > +The ISA-dependent CSR are only valid when the specific ISA is set. The > +read-only CSR can not be written by the CSR instructions. > + > Mask(64BIT) > > Mask(MUL) > diff --git a/gcc/configure.ac b/gcc/configure.ac > index 50bb61c1b61..1a9288ee659 100644 > --- a/gcc/configure.ac > +++ b/gcc/configure.ac > @@ -5269,6 +5269,11 @@ configured with --enable-newlib-nano-formatted-io.]) > [-march=rv32i_zifencei2p0],,, > [AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1, > [Define if the assembler understands -march=rv*_zifencei.])]) > + gcc_GAS_CHECK_FEATURE([-mcsr-check], > + gcc_cv_as_riscv_csr_check, > + [-mcsr-check],,, > + [AC_DEFINE(HAVE_AS_MCSR_CHECK, 1, > + [Define if the assembler understands -mcsr-check.])]) > ;; > loongarch*-*-*) > gcc_GAS_CHECK_FEATURE([.dtprelword support], > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index dd3302fcd15..7caade26b94 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -1224,6 +1224,7 @@ See RS/6000 and PowerPC Options. > -mbig-endian -mlittle-endian @gol > -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol > -mstack-protector-guard-offset=@var{offset}} > +-mcsr-check -mno-csr-check @gol > > @emph{RL78 Options} > @gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol > @@ -28551,6 +28552,11 @@ linker relaxations. > Emit (do not emit) RISC-V attribute to record extra information into ELF > objects. This feature requires at least binutils 2.32. > > +@item -mcsr-check > +@itemx -mno-csr-check > +@opindex mcsr-check > +Enables or disables the CSR checking. > + > @item -malign-data=@var{type} > @opindex malign-data > Control how GCC aligns variables and constants of array, structure, or union > -- > 2.34.1 >