From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by sourceware.org (Postfix) with ESMTPS id 42B7B3853835 for ; Thu, 6 Oct 2022 01:58:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 42B7B3853835 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x531.google.com with SMTP id e18so871874edj.3 for ; Wed, 05 Oct 2022 18:58:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=0ozp907xdRuL/uBxdJqWrIez8wVEDzP8w88ozcFm0RE=; b=LNsQ4FvRqMmGNneErh0iayF/X+dDQjoxmDtv/7DVw0sUSwyDZnCeGS5jqufSVLD+I7 HvrM+YA1HHaGV+U9kiC3AuEP4PnLDvqz+q9OBC4WyTuc7/F5EdZoQpHwufYjorQUCAXE tW62xWPzGWYY0rgvFUCTj3oKhUhSpiUKVyN2T/7SU/OOIuPRsiyABq3jLSVREeOSTyRH O7zIkkK7vAmwnLggTuzNVNyaEzZKcC6/HPFLA0fOr/TgIe5hRvtV+G7aUiiK+48OOHs8 sZtkSCPLsO0p43fc9wuBRnCMXXpu9HIrOUHTkDoUQrUqu1G8w58pGjSRSgJ90w88hhR6 bW0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=0ozp907xdRuL/uBxdJqWrIez8wVEDzP8w88ozcFm0RE=; b=p8TvyXr5H3Nd9U7TzpBzuKGI8/+Ru05jEJKYeD1gpK2I+0g/sYXxqJ1qQq6wrDbPhS LgVIKTQ2zuHxEE7xrapbLbOCdy+fZfc16xM7JdXQa3M3rfuYEEFmEgPzEMGqrI2r/dJz Ut8QaKeopSb3JjIIV2DGHOmfwuTWLGZBfmdR9DFX+3GJkrIxNCiX3ic49mDWKToT9x8l N0dxiMYUMjkEwB4BAzTGtjY9c2YFMZdlYjA55pv+ZCCcDpzDECZ79OV4QxPkE3dUiV7R lU5xiJFV12cwhkpj6oTbZvEVnX06smq79+oy+FzzC9dn5l3GXWL5VOpObE5YgqST/z0J 4NsQ== X-Gm-Message-State: ACrzQf1hMnQDDzk47VRauIXMpQypnnLtViJYfq2FF9nhK8PqovWVmEHH vLPmbao4L1Q+yhRq5OSosVAzeIv904AmSpHz1eM= X-Google-Smtp-Source: AMsMyM6M7i3XUHFTFXmMPve1ZRfirOiVBCp2OV0qMajqlBtBHMpIoDNORTlVPeAKlsTwPP7VFddicEu/eydqCnxF/p0= X-Received: by 2002:a05:6402:3718:b0:453:a46c:386c with SMTP id ek24-20020a056402371800b00453a46c386cmr2414673edb.97.1665021503518; Wed, 05 Oct 2022 18:58:23 -0700 (PDT) MIME-Version: 1.0 References: <20221005035446.30054-1-palmer@rivosinc.com> In-Reply-To: From: Kito Cheng Date: Thu, 6 Oct 2022 09:58:11 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Default to tuning for the thead-c906 To: Andrew Pinski Cc: Palmer Dabbelt , gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: -1 for this, default enable fast unaligned access could cause many problems, and lots of RISC-V cores don't support HW unaligned access (Rocket-base RISC-V core, most SiFive core, and most Andes core IIRC), change this to default means package from RISC-V linux distro might contain unaligned access by default. The default one should be the safest option, in case people really want that, they could use --with-tune and --with-arch to change that. On Wed, Oct 5, 2022 at 1:57 PM Andrew Pinski via Gcc-patches wrote: > > On Tue, Oct 4, 2022 at 8:55 PM Palmer Dabbelt wrote: > > > > The C906 is by far the most widely available RISC-V processor, so let's > > default to tuning for it. > > > > gcc/ChangeLog > > > > * config/riscv/riscv.h (RISCV_TUNE_STRING_DEFAULT): Change to > > thead-c906. > > * doc/invoke.texi (RISC-V -mtune): Change the default to > > thead-c906. > > > > --- > > I am ok with this as --with-tune and --with-arch works as ways of > changing the default still. > > Thanks, > Andrew > > > > > This has come up a handful of times, most recently during the Cauldron. > > It seems like a grey area to me: we're changing the behavior of some > > command-line arguments (ie, everything that doesn't specify -mtune), but > > we sort of change that anyway as the tuning parameters change between > > releases. > > > > I'm not really seeing much of a precedent from the other ports. It > > looks like aarch64 sort of changed the default in 02fdbd5beb0 > > ("[AArch64] [-mtune cleanup 2/5] Tune for Cortex-A53 by default.") but I > > think at that point -mtune=generic and -mtune=cortex-a53 were equivalent > > so I'm not sure that counts. I can't quite sort out if the default x86 > > tuning has ever changed, but the tuning parameters have changed. I > > don't see any way around having the tuning parameters change as they're > > pretty tightly coupled to the GCC internals, but changing to a different > > tuning target is a bit bigger of a change. > > > > We also have a bit of a special case here: -mtune is in theory only a > > performance issue, but this change will emit a lot more misaligned > > accesses and we've seen those trigger bugs in the trap handlers before. > > Those bugs are elsewhere so it's sort of not a GCC problem, but I'm sure > > there's still users out there with broken firmware and this may cause > > visible fallout. We can just tell those users their systems were always > > broken, but that's never a fun way to do things. > > > > I figured the easiest way to talk about this would be to just send the > > patch, but I definitely don't plan on committing it without some > > discussion. > > --- > > gcc/config/riscv/riscv.h | 2 +- > > gcc/doc/invoke.texi | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > > index 363113c6511..1d9379fa5ee 100644 > > --- a/gcc/config/riscv/riscv.h > > +++ b/gcc/config/riscv/riscv.h > > @@ -40,7 +40,7 @@ along with GCC; see the file COPYING3. If not see > > #endif > > > > #ifndef RISCV_TUNE_STRING_DEFAULT > > -#define RISCV_TUNE_STRING_DEFAULT "rocket" > > +#define RISCV_TUNE_STRING_DEFAULT "thead-c906" > > #endif > > > > extern const char *riscv_expand_arch (int argc, const char **argv); > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > > index e0c2c57c9b2..2a9ea3455f6 100644 > > --- a/gcc/doc/invoke.texi > > +++ b/gcc/doc/invoke.texi > > @@ -28529,7 +28529,7 @@ particular CPU name. Permissible values for this option are: @samp{rocket}, > > @samp{thead-c906}, @samp{size}, and all valid options for @option{-mcpu=}. > > > > When @option{-mtune=} is not specified, use the setting from @option{-mcpu}, > > -the default is @samp{rocket} if both are not specified. > > +the default is @samp{thead-c906} if both are not specified. > > > > The @samp{size} choice is not intended for use by end-users. This is used > > when @option{-Os} is specified. It overrides the instruction cost info > > -- > > 2.34.1 > >