From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id B3574385840F for ; Wed, 3 Jan 2024 03:32:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B3574385840F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B3574385840F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::635 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704252770; cv=none; b=Rv2T3kY4g7UN3unnID9iHe9talJPQyFq6cYrGr14d+mVfbChRMD8gecDRx+RtVRckzrrUG6fweyzlxs10pL94SAQVzBzDFGkKzCtr9/tucCBjjIpZJboNq8LzfhN2LvHVRthAn7iEkzeenFt3aykme2wgMyQ9Fby0GpRxE1FE/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704252770; c=relaxed/simple; bh=W5p5X0zcYbod7b9/wtCkoviH/LCQkwN23+lr5mMBhz4=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=BvkwDtzpYpKraSkTS/FVyUVu6gr9aHgm5gJ7lJZi8W8Y3rRJDd11od+Bnplc42S9Xr8JO0xrnga+chEQaQ+OheRkMPziFwZMmygci6/NyKb7URC59odXEXLrD6oWPnqC4Xnh8lRzbwP5dNQSmetp8CvOkEoRqk5p17K3YPxrFn0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-a2335d81693so13184466b.0 for ; Tue, 02 Jan 2024 19:32:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704252766; x=1704857566; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=rSljecaJ6cBGhsnAoViloP0a+sfp8F8+QwEjRzOZdlQ=; b=OJQQ/FK4BLfutz2Y+vxkqI3WW0Pa2v4YbHfGG2GVwJXXAjsfPiB2pdt+4XT/SetuYP RoNPCyHKFZ1UkTEfV/0AXp3rxkiy9uSEX438QfxZZlW7jI1+wVyqyvFi/aYj6rNXbsCs JgndrO2RV0+1GYc8MsPYmUVdsPNb9+SemjQEtuOmVUJWsz5oP+PzA8oHxh10oE5LLsIL taHROhZGQ+JHENPnXrP3jQRCw8Vw3oVnMNo+rE7ky8JqNmt/zDn9I/4vJKU2NzHQR84Q Y5u2kCHOIESj6yotaXAtDK+NKaLGeoApbF2HpUHkV6U7AlQQgI/HybGc6crmVqPfsK+0 SsFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704252766; x=1704857566; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rSljecaJ6cBGhsnAoViloP0a+sfp8F8+QwEjRzOZdlQ=; b=O7kwZ9cj8AFjG4420Ux17iWmneHjfxc9jz/geY7tl1/kSXmYrshR6EAS2awpImaxSI pMEnMyKOrdbdL0sDNglR4FmJtLR8lV7f5YK48A6AX3Y97vKjZE4pMUYR5vIG2AJzwRtr SFZiTEFhZz0fbPQYFR2HK5Eq9+Pq+erOAGqdrh7K2erlJxr1gT7E5Cqlp3iqu4RBEEhO oiEL9uVNTSmqzrDpVjaEikalFnvnfLxyMqodTz99nzEULUeOT3cvR0fM6iLL6oAEi48o UBlUsoPMkYUgbANmIDnFKwwOSNcLXmDrLCYP02TaKLUWsRVtPiy0dfgagVWPMpZdOMIK PEzA== X-Gm-Message-State: AOJu0Yy1wkWZbPtxm3pKr4jiJAhVFCsF8GjU0W2wt6ISI4NFKryQm7zd aRkSOWbaqkfD+5Bwn5mLO4J2bkGL9+ZBIqkcAdF3sAXHm4w0u2Sn X-Google-Smtp-Source: AGHT+IEAUts7M7vFztxg6Y48a3iAGmZXxFk8wWclE9NIS836xBuSd5Ykb78oUkWV0Id9NaK1sOfDITfu/sCTbucn6Bw= X-Received: by 2002:a17:906:1cce:b0:a27:7602:2c6a with SMTP id i14-20020a1709061cce00b00a2776022c6amr368116ejh.36.1704252766128; Tue, 02 Jan 2024 19:32:46 -0800 (PST) MIME-Version: 1.0 References: <20231229040310.1047-1-cooper.joshua@linux.alibaba.com> <20231229041943.1366-1-cooper.joshua@linux.alibaba.com> <929ccf06-d106-40a5-b5b3-050d5aaf4875@gmail.com> <27476D48F2EA4552+2024010311063870318327@rivai.ai> In-Reply-To: From: Kito Cheng Date: Wed, 3 Jan 2024 11:32:34 +0800 Message-ID: Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. To: "juzhe.zhong@rivai.ai" Cc: pinskia , jeffreyalaw , "cooper.joshua" , gcc-patches , Jim Wilson , palmer , andrew , "philipp.tomsich" , "christoph.muellner" , jinma , "cooper.qu" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Andrew: That's kinda compromise and trade off on the t-head vector stuffs, we would like to accept that, but without disturbing the vector 1.0 implementation too much, t-head vector is transitional product and it will freeze/stop there forever without extending new stuffs like vector bfloat and vector crypto stuffs. So we think using ASM_OUTPUT_OPCODE is better in this case rather than adding %^ to every vector pattern for the t-head vector. On Wed, Jan 3, 2024 at 11:26=E2=80=AFAM juzhe.zhong@rivai.ai wrote: > > No. It will need to change all patterns in vector.md. > It's a nightmare. > > You should note I will refine vector.md in GCC-15, mixing theadvector thi= ngs make me impossible to maintain > RVV1.0. > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Andrew Pinski > Date: 2024-01-03 11:19 > To: juzhe.zhong@rivai.ai > CC: jeffreyalaw; cooper.joshua; gcc-patches; Jim Wilson; palmer; andrew; = philipp.tomsich; christoph.muellner; jinma; cooper.qu > Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instruc= tions of XTheadVector. > On Tue, Jan 2, 2024 at 7:07=E2=80=AFPM juzhe.zhong@rivai.ai > wrote: > > > > We have no choice. You should know theadvector is totally unrelated wit= h RVV1.0 standard ISA. > > > > Adding `%^' which missing totally unrelated ISA makes no sens to me. > > No, it implements it in a different way. > Basically all of the patterns which are supported get changed to be > instead of "v*" becomes instead "%^v" and then you change > riscv_print_operand_punct_valid_p to allow '^' and then you add '^' > support to riscv_print_operand (like '~' is handled there). > > And the next patch adds a few more '%' to support printing different > different strings based on XTheadVector or not. > > This is how almost all other targets handle this kind of things > instead of hacking ASM_OUTPUT_OPCODE . > > Thanks, > Andrew Pinski > > > > > > ________________________________ > > juzhe.zhong@rivai.ai > > > > > > From: Andrew Pinski > > Date: 2024-01-03 10:54 > > To: =E9=92=9F=E5=B1=85=E5=93=B2 > > CC: Jeff Law; cooper.joshua; gcc-patches; jim.wilson.gcc; palmer; andre= w; philipp.tomsich; Christoph M=C3=BCllner; jinma; Cooper Qu > > Subject: Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instr= uctions of XTheadVector. > > On Mon, Jan 1, 2024 at 2:59=E2=80=AFPM =E9=92=9F=E5=B1=85=E5=93=B2 wrote: > > > > > > This is Ok from my side. > > > But before commit this patch, I think we need this patch first: > > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html > > > > > > I will be back to work so I will take a look at other patches today. > > > > > > Note I hate it. It would be better if you use something like `%^' (see > > `~` for an example of how that works) instead of hacking > > riscv_asm_output_opcode really. In fact that is how other targets > > implement this kind of things. > > > > Thanks, > > Andrew PInski > > > > > ________________________________ > > > juzhe.zhong@rivai.ai > > > > > > > > > From: Jeff Law > > > Date: 2024-01-01 01:43 > > > To: Jun Sha (Joshua); gcc-patches > > > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muelln= er; juzhe.zhong; Jin Ma; Xianmiao Qu > > > Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instruc= tions of XTheadVector. > > > > > > > > > On 12/28/23 21:19, Jun Sha (Joshua) wrote: > > > > This patch adds th. prefix to all XTheadVector instructions by > > > > implementing new assembly output functions. We only check the > > > > prefix is 'v', so that no extra attribute is needed. > > > > > > > > gcc/ChangeLog: > > > > > > > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode): > > > > New function to add assembler insn code prefix/suffix. > > > > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. > > > > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise. > > > > > > > > Co-authored-by: Jin Ma > > > > Co-authored-by: Xianmiao Qu > > > > Co-authored-by: Christoph M=C3=BCllner > > > > --- > > > > gcc/config/riscv/riscv-protos.h | 1 + > > > > gcc/config/riscv/riscv.cc | 14 +++++++++= +++++ > > > > gcc/config/riscv/riscv.h | 4 ++++ > > > > .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 +++++++++= +++ > > > > 4 files changed, 31 insertions(+) > > > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvecto= r/prefix.c > > > > > > > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/ris= cv-protos.h > > > > index 31049ef7523..5ea54b45703 100644 > > > > --- a/gcc/config/riscv/riscv-protos.h > > > > +++ b/gcc/config/riscv/riscv-protos.h > > > > @@ -102,6 +102,7 @@ struct riscv_address_info { > > > > }; > > > > > > > > /* Routines implemented in riscv.cc. */ > > > > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, co= nst char *p); > > > > extern enum riscv_symbol_type riscv_classify_symbolic_expression = (rtx); > > > > extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_typ= e *); > > > > extern int riscv_float_const_rtx_index_for_fli (rtx); > > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > > > index 0d1cbc5cb5f..ea1d59d9cf2 100644 > > > > --- a/gcc/config/riscv/riscv.cc > > > > +++ b/gcc/config/riscv/riscv.cc > > > > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mo= de) > > > > return lmul; > > > > } > > > > > > > > +/* Define ASM_OUTPUT_OPCODE to do anything special before > > > > + emitting an opcode. */ > > > > +const char * > > > > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) > > > > +{ > > > > + /* We need to add th. prefix to all the xtheadvector > > > > + insturctions here.*/ > > > > + if (TARGET_XTHEADVECTOR && current_output_insn !=3D NULL_RTX && > > > > + p[0] =3D=3D 'v') > > > > + fputs ("th.", asm_out_file); > > > > + > > > > + return p; > > > Just a formatting nit. The GNU standards break lines before the > > > operator, not after. So > > > if (TARGET_XTHEADVECTOR > > > && current_output_insn !=3D NULL > > > && p[0] =3D=3D 'v') > > > > > > Note that current_output_insn is "extern rtx_insn *", so use NULL, no= t > > > NULL_RTX. > > > > > > Neither of these nits require a new version for review. Just fix the= m. > > > > > > If Juzhe is fine with this, so am I. We can refine it if necessary l= ater. > > > > > > jeff > > > > > >