From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe31.google.com (mail-vs1-xe31.google.com [IPv6:2607:f8b0:4864:20::e31]) by sourceware.org (Postfix) with ESMTPS id E530A3852219 for ; Mon, 19 Dec 2022 15:08:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E530A3852219 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe31.google.com with SMTP id 128so8924519vsz.12 for ; Mon, 19 Dec 2022 07:08:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=3nIHJvLLoICBECgt5/NF7eMvrQp/KfrvNfM2quEnSF8=; b=i5IZKDU2wZUyUdHaqdRKqdkdhgG1zvgurfQY0BKM9WQCSJa4XoviaYDuLYKOnfQz80 5n5GrF9mO3pfF+FVZBZI1M9kwuQV0jlHawP7/qIL1Olw6naVp23YEL+xeIvPhWLGYnub q1ISIrPucXRtPjdvimCsoZ401Kmk9vFta2oeC1zcb3ltAZIR8tRIMPuNJABiTPKfplFc IwKCgPtbMhElnTQAS7BQsBO8cfZeWCdJZYX8UyRbfeI5DSHmDwml5A3ezKe3raWV2kTI DM3WIr3w9irgpxlazM0ypyjg6SXi4sxqrbEx0JIQfGyttqsSD/6HM3c/l7+9IoNIqUdv B8NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=3nIHJvLLoICBECgt5/NF7eMvrQp/KfrvNfM2quEnSF8=; b=2ZGwPCmV6PyT4638XVZTX30m8l3k+hIWpqsHYI2xv7hxCRNV47qzXnoI80FchdJJwJ LmCjb/MkYP/M04aicW4tKFaZO6T2DUpQmi+CHC3nPOj+VNyld5CMEc5z5VJsVL25zq1+ No43PuNAvwY8slfki681jBt+Yg1keXZTnUlGJeyCnuGY8phFElhaY5YVhLs3w4pc408j ef5IhFzHL4gMYl80hv6RlHmE/X4MJ+2ccpdi9VAncaa2NxTZY+Dj9PA1LqX1GVJhPF4E 9rxbxaCUDjKUrDg+iQ4drvOhD77rT4UQcOjMKPEnXgbAu3jv3uISK3Jtef+tMmUxZdd5 Yy4g== X-Gm-Message-State: ANoB5plrudMBH76Kx14qlbUHIo1Rgcrk6jFVwJ5KnKtRQjd0jC2LkDPn iKyGt1dDhaJrb8KcHQnRpjKKTJuUvqgyN7IFsJQ= X-Google-Smtp-Source: AA0mqf70/LO1udUcIOF2PLDeykVkbLD5Xf/W8iHXON7y9BQFTisVU0UNKFnmeWoopvlsfp0xYIG8kWgGtCBJVVQuAjw= X-Received: by 2002:a05:6102:2c9:b0:3b2:e5b1:5a63 with SMTP id h9-20020a05610202c900b003b2e5b15a63mr12376315vsh.84.1671462529681; Mon, 19 Dec 2022 07:08:49 -0800 (PST) MIME-Version: 1.0 References: <20221214074656.217538-1-juzhe.zhong@rivai.ai> In-Reply-To: <20221214074656.217538-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Mon, 19 Dec 2022 23:08:36 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add VSETVL PASS VLMAX testcases. To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: GCC Patches , Palmer Dabbelt Content-Type: multipart/alternative; boundary="000000000000564ee805f02fb21e" X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000564ee805f02fb21e Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Commited to trunk =E6=96=BC 2022=E5=B9=B412=E6=9C=8814=E6=97=A5 =E9=80= =B1=E4=B8=89 15:46 =E5=AF=AB=E9=81=93=EF=BC=9A > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/rvv.exp: Adjust to enable tests for VSETVL > PASS. > * gcc.target/riscv/rvv/vsetvl/dump-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: New test. > > --- > gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + > .../gcc.target/riscv/rvv/vsetvl/dump-1.c | 33 + > .../riscv/rvv/vsetvl/vlmax_back_prop-1.c | 36 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-10.c | 59 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-11.c | 63 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-12.c | 64 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-13.c | 64 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-14.c | 58 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-15.c | 143 +++++ > .../riscv/rvv/vsetvl/vlmax_back_prop-16.c | 54 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-17.c | 59 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-18.c | 58 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-19.c | 48 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-2.c | 50 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-20.c | 59 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-21.c | 50 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-22.c | 58 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-23.c | 41 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-24.c | 41 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-25.c | 96 +++ > .../riscv/rvv/vsetvl/vlmax_back_prop-26.c | 89 +++ > .../riscv/rvv/vsetvl/vlmax_back_prop-27.c | 51 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-28.c | 54 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-29.c | 54 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-3.c | 47 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-30.c | 44 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-31.c | 46 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-32.c | 46 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-33.c | 45 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-34.c | 45 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-35.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-36.c | 47 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-37.c | 41 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-38.c | 73 +++ > .../riscv/rvv/vsetvl/vlmax_back_prop-39.c | 20 + > .../riscv/rvv/vsetvl/vlmax_back_prop-4.c | 104 ++++ > .../riscv/rvv/vsetvl/vlmax_back_prop-40.c | 22 + > .../riscv/rvv/vsetvl/vlmax_back_prop-41.c | 26 + > .../riscv/rvv/vsetvl/vlmax_back_prop-42.c | 26 + > .../riscv/rvv/vsetvl/vlmax_back_prop-43.c | 27 + > .../riscv/rvv/vsetvl/vlmax_back_prop-44.c | 28 + > .../riscv/rvv/vsetvl/vlmax_back_prop-45.c | 34 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-46.c | 32 + > .../riscv/rvv/vsetvl/vlmax_back_prop-5.c | 48 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-6.c | 155 +++++ > .../riscv/rvv/vsetvl/vlmax_back_prop-7.c | 43 ++ > .../riscv/rvv/vsetvl/vlmax_back_prop-8.c | 149 +++++ > .../riscv/rvv/vsetvl/vlmax_back_prop-9.c | 44 ++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-1.c | 182 ++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-10.c | 230 +++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-11.c | 43 ++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-12.c | 266 ++++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-13.c | 221 +++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-14.c | 221 +++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-15.c | 41 ++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-16.c | 257 ++++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-17.c | 177 ++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-18.c | 177 ++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-19.c | 34 ++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-2.c | 182 ++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-20.c | 203 +++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-21.c | 155 +++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-22.c | 155 +++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-23.c | 30 + > .../riscv/rvv/vsetvl/vlmax_bb_prop-24.c | 180 ++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-25.c | 572 ++++++++++++++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-26.c | 492 +++++++++++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-27.c | 491 +++++++++++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-28.c | 86 +++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-3.c | 35 ++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-4.c | 210 +++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-5.c | 167 +++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-6.c | 167 +++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-7.c | 32 + > .../riscv/rvv/vsetvl/vlmax_bb_prop-8.c | 194 ++++++ > .../riscv/rvv/vsetvl/vlmax_bb_prop-9.c | 230 +++++++ > .../riscv/rvv/vsetvl/vlmax_call-1.c | 239 ++++++++ > .../riscv/rvv/vsetvl/vlmax_call-2.c | 207 +++++++ > .../riscv/rvv/vsetvl/vlmax_call-3.c | 207 +++++++ > .../riscv/rvv/vsetvl/vlmax_call-4.c | 39 ++ > .../riscv/rvv/vsetvl/vlmax_complex_loop-1.c | 52 ++ > .../riscv/rvv/vsetvl/vlmax_complex_loop-2.c | 56 ++ > .../riscv/rvv/vsetvl/vlmax_conflict-1.c | 23 + > .../riscv/rvv/vsetvl/vlmax_conflict-10.c | 27 + > .../riscv/rvv/vsetvl/vlmax_conflict-11.c | 24 + > .../riscv/rvv/vsetvl/vlmax_conflict-12.c | 39 ++ > .../riscv/rvv/vsetvl/vlmax_conflict-2.c | 23 + > .../riscv/rvv/vsetvl/vlmax_conflict-3.c | 30 + > .../riscv/rvv/vsetvl/vlmax_conflict-4.c | 29 + > .../riscv/rvv/vsetvl/vlmax_conflict-5.c | 32 + > .../riscv/rvv/vsetvl/vlmax_conflict-6.c | 26 + > .../riscv/rvv/vsetvl/vlmax_conflict-7.c | 26 + > .../riscv/rvv/vsetvl/vlmax_conflict-8.c | 27 + > .../riscv/rvv/vsetvl/vlmax_conflict-9.c | 27 + > .../riscv/rvv/vsetvl/vlmax_miss_default-1.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-10.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-11.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-12.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-13.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-14.c | 189 ++++++ > .../riscv/rvv/vsetvl/vlmax_miss_default-15.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-16.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-17.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-18.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-19.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-2.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-20.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-21.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-22.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-23.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-24.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-25.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-26.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-27.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_miss_default-28.c | 231 +++++++ > .../riscv/rvv/vsetvl/vlmax_miss_default-3.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-4.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-5.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-6.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-7.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-8.c | 32 + > .../riscv/rvv/vsetvl/vlmax_miss_default-9.c | 32 + > .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c | 37 ++ > .../riscv/rvv/vsetvl/vlmax_phi-10.c | 37 ++ > .../riscv/rvv/vsetvl/vlmax_phi-11.c | 37 ++ > .../riscv/rvv/vsetvl/vlmax_phi-12.c | 37 ++ > .../riscv/rvv/vsetvl/vlmax_phi-13.c | 37 ++ > .../riscv/rvv/vsetvl/vlmax_phi-14.c | 217 +++++++ > .../riscv/rvv/vsetvl/vlmax_phi-15.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-16.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-17.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-18.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-19.c | 40 ++ > .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c | 37 ++ > .../riscv/rvv/vsetvl/vlmax_phi-20.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-21.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-22.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-23.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-24.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-25.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-26.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-27.c | 40 ++ > .../riscv/rvv/vsetvl/vlmax_phi-28.c | 237 ++++++++ > .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c | 37 ++ > .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c | 37 ++ > .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c | 37 ++ > .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c | 37 ++ > .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c | 37 ++ > .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c | 37 ++ > .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c | 37 ++ > .../riscv/rvv/vsetvl/vlmax_single_block-1.c | 154 +++++ > .../riscv/rvv/vsetvl/vlmax_single_block-10.c | 143 +++++ > .../riscv/rvv/vsetvl/vlmax_single_block-11.c | 34 ++ > .../riscv/rvv/vsetvl/vlmax_single_block-12.c | 92 +++ > .../riscv/rvv/vsetvl/vlmax_single_block-13.c | 89 +++ > .../riscv/rvv/vsetvl/vlmax_single_block-14.c | 16 + > .../riscv/rvv/vsetvl/vlmax_single_block-15.c | 42 ++ > .../riscv/rvv/vsetvl/vlmax_single_block-16.c | 147 +++++ > .../riscv/rvv/vsetvl/vlmax_single_block-17.c | 32 + > .../riscv/rvv/vsetvl/vlmax_single_block-18.c | 32 + > .../riscv/rvv/vsetvl/vlmax_single_block-19.c | 105 ++++ > .../riscv/rvv/vsetvl/vlmax_single_block-2.c | 70 +++ > .../riscv/rvv/vsetvl/vlmax_single_block-3.c | 70 +++ > .../riscv/rvv/vsetvl/vlmax_single_block-4.c | 49 ++ > .../riscv/rvv/vsetvl/vlmax_single_block-5.c | 49 ++ > .../riscv/rvv/vsetvl/vlmax_single_block-6.c | 28 + > .../riscv/rvv/vsetvl/vlmax_single_block-7.c | 28 + > .../riscv/rvv/vsetvl/vlmax_single_block-8.c | 28 + > .../riscv/rvv/vsetvl/vlmax_single_block-9.c | 147 +++++ > .../riscv/rvv/vsetvl/vlmax_single_vtype-1.c | 86 +++ > .../riscv/rvv/vsetvl/vlmax_single_vtype-2.c | 42 ++ > .../riscv/rvv/vsetvl/vlmax_single_vtype-3.c | 38 ++ > .../riscv/rvv/vsetvl/vlmax_single_vtype-4.c | 31 + > .../riscv/rvv/vsetvl/vlmax_single_vtype-5.c | 31 + > .../riscv/rvv/vsetvl/vlmax_single_vtype-6.c | 18 + > .../riscv/rvv/vsetvl/vlmax_single_vtype-7.c | 18 + > .../riscv/rvv/vsetvl/vlmax_single_vtype-8.c | 18 + > .../riscv/rvv/vsetvl/vlmax_switch_vtype-1.c | 26 + > .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 47 ++ > .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 55 ++ > .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 55 ++ > .../riscv/rvv/vsetvl/vlmax_switch_vtype-13.c | 17 + > .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c | 39 ++ > .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c | 52 ++ > .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c | 60 ++ > .../riscv/rvv/vsetvl/vlmax_switch_vtype-2.c | 26 + > .../riscv/rvv/vsetvl/vlmax_switch_vtype-3.c | 25 + > .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 20 + > .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 20 + > .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 33 + > .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 43 ++ > .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 45 ++ > .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 45 ++ > 193 files changed, 14207 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1= .c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2= .c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9= .c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > index 25e09f41d73..2ed29e22606 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > @@ -42,6 +42,8 @@ dg-init > set CFLAGS "$DEFAULT_CFLAGS -march=3D$gcc_march -O3" > dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ > "" $CFLAGS > +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] > \ > + "" $CFLAGS > > # All done. > dg-finish > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c > new file mode 100644 > index 00000000000..fb4edb459a0 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c > @@ -0,0 +1,33 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fdump-rtl-vsetvl-detail= s" } > */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, void * restrict in2, > void * restrict out2, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) > + { > + vuint16mf4_t v2; > + *(vuint16mf4_t*)(out + i + 1000) =3D v2; > + vbool32_t v4; > + *(vbool32_t*)(out + i + 3000) =3D v4; > + vbool16_t v5; > + *(vbool16_t*)(out + i + 4000) =3D v5; > + vbool8_t v6; > + *(vbool8_t*)(out + i + 5000) =3D v6; > + vbool4_t v7; > + *(vbool4_t*)(out + i + 6000) =3D v7; > + vbool2_t v8; > + *(vbool2_t*)(out + i + 7000) =3D v8; > + vbool1_t v9; > + *(vbool1_t*)(out + i + 8000) =3D v9; > + vuint32mf2_t v10; > + *(vuint32mf2_t*)(out + i + 100000) =3D v10; > + } > + > + for (int i =3D 0; i < n; i++) > + { > + vint8mf8_t v1 =3D *(vint8mf8_t*)(in + i + 100000); > + *(vint8mf8_t*)(out + i + 10) =3D v1; > + } > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c > new file mode 100644 > index 00000000000..47645ee7110 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c > @@ -0,0 +1,36 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } > */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts > "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c > new file mode 100644 > index 00000000000..d36df955a43 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c > @@ -0,0 +1,59 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, > int cond2, int cond3) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) > + { > + if (cond2 =3D=3D 11) > + { > + for (int i =3D 0; i < n; i++) > + { > + out[i] =3D out[i] + 2; > + } > + } > + else if (cond2 =3D=3D 111) > + { > + if (cond3 =3D=3D 300) > + { > + for (int i =3D 0; i < n; i++) > + { > + out[i] =3D out[i] + out[i]; > + } > + } > + } > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" > no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } }= */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c > new file mode 100644 > index 00000000000..fa818aa3b1c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c > @@ -0,0 +1,63 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, > int cond2, int cond3) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + i); > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200 + i); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300 + i); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400 + i); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500 + i); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) > + { > + if (cond2 =3D=3D 11) > + { > + for (int i =3D 0; i < n; i++) > + { > + out[i] =3D out[i] + 2; > + } > + } > + else if (cond2 =3D=3D 111) > + { > + if (cond3 =3D=3D 300) > + { > + for (int i =3D 0; i < n; i++) > + { > + out[i] =3D out[i] + out[i]; > + } > + } else { > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 2000 + i); > + *(vfloat32mf2_t*)(out + i + 4000) =3D v; > + } > + } > + } > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" > no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } }= */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c > new file mode 100644 > index 00000000000..324e38d3fc6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c > @@ -0,0 +1,64 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, > int cond2, int cond3) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + i); > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200 + i); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300 + i); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400 + i); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500 + i); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) > + { > + if (cond2 =3D=3D 11) > + { > + for (int i =3D 0; i < n; i++) > + { > + out[i] =3D out[i] + 2; > + } > + } > + else if (cond2 =3D=3D 111) > + { > + if (cond3 =3D=3D 300) > + { > + for (int i =3D 0; i < n; i++) > + { > + out[i] =3D out[i] + out[i]; > + } > + } else { > + for (int i =3D 0; i < n; i++) { > + vint8mf2_t v =3D *(vint8mf2_t*)(in + 2000 + i); > + *(vint8mf2_t*)(out + i + 4000) =3D v; > + } > + } > + } > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf4,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" no-opts "-flto" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" > no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts > "-flto" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c > new file mode 100644 > index 00000000000..23d21557d03 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c > @@ -0,0 +1,64 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, > int cond2, int cond3) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + i); > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200 + i); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300 + i); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400 + i); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500 + i); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) > + { > + if (cond2 =3D=3D 11) > + { > + for (int i =3D 0; i < n; i++) > + { > + out[i] =3D out[i] + 2; > + } > + } > + else if (cond2 =3D=3D 111) > + { > + if (cond3 =3D=3D 300) > + { > + for (int i =3D 0; i < n; i++) > + { > + out[i] =3D out[i] + out[i]; > + } > + } else { > + for (int i =3D 0; i < n; i++) { > + vint8mf2_t v =3D *(vint8mf2_t*)(in + 2000 + i); > + *(vint8mf2_t*)(out + i + 4000) =3D v; > + } > + } > + } > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16m1_t v; > + *(vint16m1_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" no-opts "-flto" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= m1,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" > no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts > "-flto" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c > new file mode 100644 > index 00000000000..da48ce2f1f3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c > @@ -0,0 +1,58 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333); > + *(vint8mf8_t*)(out + i + 333) =3D v; > + } > + } else if (cond =3D=3D 1){ > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 444); > + *(vint32mf2_t*)(out + i + 444) =3D v; > + } > + } else if (cond =3D=3D 2) { > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 555); > + *(vint64m1_t*)(out + i + 555) =3D v; > + } > + } else { > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 666); > + *(vfloat64m1_t*)(out + i + 666) =3D v; > + } > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c > new file mode 100644 > index 00000000000..7dd931c9df8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c > @@ -0,0 +1,143 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333); > + *(vint8mf8_t*)(out + i + 333) =3D v; > + } > + } else if (cond =3D=3D 1){ > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 444); > + *(vint32mf2_t*)(out + i + 444) =3D v; > + } > + } else if (cond =3D=3D 2) { > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 555); > + *(vint64m1_t*)(out + i + 555) =3D v; > + } > + } else { > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 666); > + *(vfloat64m1_t*)(out + i + 666) =3D v; > + } > + } > + > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333); > + *(vint8mf8_t*)(out + i + 333) =3D v; > + } > + } else if (cond =3D=3D 1){ > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 444); > + *(vint32mf2_t*)(out + i + 444) =3D v; > + } > + } else if (cond =3D=3D 2) { > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 555); > + *(vint64m1_t*)(out + i + 555) =3D v; > + } > + } else { > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 666); > + *(vfloat64m1_t*)(out + i + 666) =3D v; > + } > + } > + > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333); > + *(vint8mf8_t*)(out + i + 333) =3D v; > + } > + } else if (cond =3D=3D 1){ > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 444); > + *(vint32mf2_t*)(out + i + 444) =3D v; > + } > + } else if (cond =3D=3D 2) { > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 555); > + *(vint64m1_t*)(out + i + 555) =3D v; > + } > + } else { > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 666); > + *(vfloat64m1_t*)(out + i + 666) =3D v; > + } > + } > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333); > + *(vint8mf8_t*)(out + i + 333) =3D v; > + } > + } else if (cond =3D=3D 1){ > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 444); > + *(vint32mf2_t*)(out + i + 444) =3D v; > + } > + } else if (cond =3D=3D 2) { > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 555); > + *(vint64m1_t*)(out + i + 555) =3D v; > + } > + } else { > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 666); > + *(vfloat64m1_t*)(out + i + 666) =3D v; > + } > + } > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333); > + *(vint8mf8_t*)(out + i + 333) =3D v; > + } > + } else if (cond =3D=3D 1){ > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 444); > + *(vint32mf2_t*)(out + i + 444) =3D v; > + } > + } else if (cond =3D=3D 2) { > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 555); > + *(vint64m1_t*)(out + i + 555) =3D v; > + } > + } else { > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 666); > + *(vfloat64m1_t*)(out + i + 666) =3D v; > + } > + } > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c > new file mode 100644 > index 00000000000..84abe55a2b0 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c > @@ -0,0 +1,54 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 771); > + *(vint8mf8_t*)(out + 771) =3D v; > + vint32mf2_t v2 =3D *(vint32mf2_t*)(in + 71); > + *(vint32mf2_t*)(out + 71) =3D v2; > + vfloat32mf2_t v3 =3D *(vfloat32mf2_t*)(in + 17); > + *(vfloat32mf2_t*)(out + 17) =3D v3; > + vuint32mf2_t v4 =3D *(vuint32mf2_t*)(in + 117); > + *(vuint32mf2_t*)(out + 117) =3D v4; > + } else { > + vfloat32mf2_t v0 =3D *(vfloat32mf2_t*)(in + 1123); > + *(vfloat32mf2_t*)(out + 1123) =3D v0; > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333); > + *(vint8mf8_t*)(out + 333) =3D v; > + vbool64_t v2 =3D *(vbool64_t*)(in + 91); > + *(vbool64_t*)(out + 91) =3D v2; > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" > no-opts "-g" no-opts "-flto" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c > new file mode 100644 > index 00000000000..dce21cc8dbc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c > @@ -0,0 +1,59 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++){ > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 771 + i); > + *(vint8mf8_t*)(out + 771 + i) =3D v; > + vint32mf2_t v2 =3D *(vint32mf2_t*)(in + 71 + i); > + *(vint32mf2_t*)(out + 71 + i) =3D v2; > + vfloat32mf2_t v3 =3D *(vfloat32mf2_t*)(in + 17 + i); > + *(vfloat32mf2_t*)(out + 17 + i) =3D v3; > + vuint32mf2_t v4 =3D *(vuint32mf2_t*)(in + 117 + i); > + *(vuint32mf2_t*)(out + 117 + i) =3D v4; > + } > + } else { > + for (int i =3D 0; i < n; i++){ > + vfloat32mf2_t v0 =3D *(vfloat32mf2_t*)(in + 1123 + i); > + *(vfloat32mf2_t*)(out + 1123 + i) =3D v0; > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333 + i); > + *(vint8mf8_t*)(out + 333 + i) =3D v; > + vbool64_t v2 =3D *(vbool64_t*)(in + 91 + i); > + *(vbool64_t*)(out + 91 + i) =3D v2; > + } > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c > new file mode 100644 > index 00000000000..18c44d6479d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c > @@ -0,0 +1,58 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++){ > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 771 + i); > + *(vint8mf8_t*)(out + 771 + i) =3D v; > + vint32mf2_t v2 =3D *(vint32mf2_t*)(in + 71 + i); > + *(vint32mf2_t*)(out + 71 + i) =3D v2; > + vfloat32mf2_t v3 =3D *(vfloat32mf2_t*)(in + 17 + i); > + *(vfloat32mf2_t*)(out + 17 + i) =3D v3; > + vuint32mf2_t v4 =3D *(vuint32mf2_t*)(in + 117 + i); > + *(vuint32mf2_t*)(out + 117 + i) =3D v4; > + } > + } else { > + vfloat32mf2_t v0 =3D *(vfloat32mf2_t*)(in + 1123); > + *(vfloat32mf2_t*)(out + 1123) =3D v0; > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333); > + *(vint8mf8_t*)(out + 333) =3D v; > + vbool64_t v2 =3D *(vbool64_t*)(in + 91); > + *(vbool64_t*)(out + 91) =3D v2; > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c > new file mode 100644 > index 00000000000..0c6a572671a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c > @@ -0,0 +1,48 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 771); > + *(vint8mf8_t*)(out + 771) =3D v; > + vint32mf2_t v2 =3D *(vint32mf2_t*)(in + 71); > + *(vint32mf2_t*)(out + 71) =3D v2; > + vfloat32mf2_t v3 =3D *(vfloat32mf2_t*)(in + 17); > + *(vfloat32mf2_t*)(out + 17) =3D v3; > + vuint32mf2_t v4 =3D *(vuint32mf2_t*)(in + 117); > + *(vuint32mf2_t*)(out + 117) =3D v4; > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } > */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c > new file mode 100644 > index 00000000000..3e7d8f4030f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c > @@ -0,0 +1,50 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + out[i] =3D out[i] + 2; > + } > + for (int i =3D 0; i < n; i++) { > + out[i] =3D out[i] + out[i]; > + } > + for (int i =3D 0; i < n; i++) { > + out[i] =3D out[i] * 2; > + } > + for (int i =3D 0; i < n; i++) { > + out[i] =3D out[i] * out[i]; > + } > + for (int i =3D 0; i < n; i++) { > + out[i] =3D out[i] * out[i] + 100; > + } > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } > */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts > "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c > new file mode 100644 > index 00000000000..dce21cc8dbc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c > @@ -0,0 +1,59 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++){ > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 771 + i); > + *(vint8mf8_t*)(out + 771 + i) =3D v; > + vint32mf2_t v2 =3D *(vint32mf2_t*)(in + 71 + i); > + *(vint32mf2_t*)(out + 71 + i) =3D v2; > + vfloat32mf2_t v3 =3D *(vfloat32mf2_t*)(in + 17 + i); > + *(vfloat32mf2_t*)(out + 17 + i) =3D v3; > + vuint32mf2_t v4 =3D *(vuint32mf2_t*)(in + 117 + i); > + *(vuint32mf2_t*)(out + 117 + i) =3D v4; > + } > + } else { > + for (int i =3D 0; i < n; i++){ > + vfloat32mf2_t v0 =3D *(vfloat32mf2_t*)(in + 1123 + i); > + *(vfloat32mf2_t*)(out + 1123 + i) =3D v0; > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333 + i); > + *(vint8mf8_t*)(out + 333 + i) =3D v; > + vbool64_t v2 =3D *(vbool64_t*)(in + 91 + i); > + *(vbool64_t*)(out + 91 + i) =3D v2; > + } > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c > new file mode 100644 > index 00000000000..7c2435ab726 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c > @@ -0,0 +1,50 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++){ > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 771 + i); > + *(vint8mf8_t*)(out + 771 + i) =3D v; > + vint32mf2_t v2 =3D *(vint32mf2_t*)(in + 71 + i); > + *(vint32mf2_t*)(out + 71 + i) =3D v2; > + vfloat32mf2_t v3 =3D *(vfloat32mf2_t*)(in + 17 + i); > + *(vfloat32mf2_t*)(out + 17 + i) =3D v3; > + vuint32mf2_t v4 =3D *(vuint32mf2_t*)(in + 117 + i); > + *(vuint32mf2_t*)(out + 117 + i) =3D v4; > + } > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c > new file mode 100644 > index 00000000000..222e0c6cbee > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c > @@ -0,0 +1,58 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + if (cond =3D=3D 0) { > + for (int i =3D 0; i < n; i++){ > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 771 + i); > + *(vint8mf8_t*)(out + 771 + i) =3D v; > + vint32mf2_t v2 =3D *(vint32mf2_t*)(in + 71 + i); > + *(vint32mf2_t*)(out + 71 + i) =3D v2; > + vfloat32mf2_t v3 =3D *(vfloat32mf2_t*)(in + 17 + i); > + *(vfloat32mf2_t*)(out + 17 + i) =3D v3; > + vuint32mf2_t v4 =3D *(vuint32mf2_t*)(in + 117 + i); > + *(vuint32mf2_t*)(out + 117 + i) =3D v4; > + } > + } else { > + vfloat32mf2_t v0 =3D *(vfloat32mf2_t*)(in + 1123); > + *(vfloat32mf2_t*)(out + 1123) =3D v0; > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 333); > + *(vint8mf8_t*)(out + 333) =3D v; > + vbool64_t v2 =3D *(vbool64_t*)(in + 91); > + *(vbool64_t*)(out + 91) =3D v2; > + } > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c > new file mode 100644 > index 00000000000..1dd55cdbb0d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c > @@ -0,0 +1,41 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + vint32mf2_t v; > + *(vint32mf2_t*)(out + 7000) =3D v; > + > + for (int i =3D 0; i < n; i++) { > + vint16mf4_t v; > + *(vint16mf4_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c > new file mode 100644 > index 00000000000..931bba5389d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c > @@ -0,0 +1,41 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (int32_t * restrict in, int32_t * restrict out, int n, int cond) > +{ > + for (int i =3D 0; i < n; i++) { > + vint8mf8_t v =3D *(vint8mf8_t*)in; > + *(vint8mf8_t*)(out + i + 200) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vint64m1_t v =3D *(vint64m1_t*)(in + 300); > + *(vint64m1_t*)(out + i + 400) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 400); > + *(vfloat32mf2_t*)(out + i + 500) =3D v; > + } > + for (int i =3D 0; i < n; i++) { > + vfloat64m1_t v =3D *(vfloat64m1_t*)(in + 500); > + *(vfloat64m1_t*)(out + i + 600) =3D v; > + } > + > + vint32mf2_t v; > + *(vint32mf2_t*)(out + 7000) =3D v; > + > + for (int i =3D 0; i < n; i++) { > + vbool64_t v; > + *(vbool64_t*)(out + i + 700) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts > "-funroll-loops" no-opts "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { > no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts > "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"= } > } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c > new file mode 100644 > index 00000000000..93015e0c5f5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c > @@ -0,0 +1,96 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32 -fno-tree-vectorize" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 0) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 100); > + *(vint8mf8_t*)(out + 100) =3D v; > + for (int i =3D 0; i < n; i++) > + { > + vint16mf4_t v2; > + *(vint16mf4_t*)(out + i + 100) =3D v2; > + } > + } else if (cond =3D=3D 1) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 200); > + *(vint8mf8_t*)(out + 200) =3D v; > + for (int i =3D 0; i < n; i++) > + { > + vint32mf2_t v2; > + *(vint32mf2_t*)(out + i + 200) =3D v2; > + } > + } else if (cond =3D=3D 2) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 300); > + *(vint8mf8_t*)(out + 300) =3D v; > + for (int i =3D 0; i < n; i++) > + { > + vint8mf8_t v2; > + *(vint8mf8_t*)(out + i + 300) =3D v2; > + } > + } else if (cond =3D=3D 3) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 400); > + *(vint8mf8_t*)(out + 400) =3D v; > + for (int i =3D 0; i < n; i++) > + { > + vint64m1_t v2; > + *(vint64m1_t*)(out + i + 400) =3D v2; > + } > + } else if (cond =3D=3D 4) { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 500); > + *(vint8mf8_t*)(out + 500) =3D v; > + for (int i =3D 0; i < n; i++) > + { > + vfloat32mf2_t v2; > + *(vfloat32mf2_t*)(out + i + 500) =3D v2; > + } > + } else if (cond =3D=3D 5) { > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + 600); > + *(vuint8mf8_t*)(out + 600) =3D v; > + for (int i =3D 0; i < n; i++) > + { > + vuint16mf4_t v2; > + *(vuint16mf4_t*)(out + i + 600) =3D v2; > + } > + } else if (cond =3D=3D 6) { > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + 700); > + *(vuint8mf8_t*)(out + 700) =3D v; > + for (int i =3D 0; i < n; --000000000000564ee805f02fb21e--