From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe33.google.com (mail-vs1-xe33.google.com [IPv6:2607:f8b0:4864:20::e33]) by sourceware.org (Postfix) with ESMTPS id DC09D3858024 for ; Wed, 6 Sep 2023 23:23:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC09D3858024 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe33.google.com with SMTP id ada2fe7eead31-44d4cef5effso142362137.1 for ; Wed, 06 Sep 2023 16:23:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694042625; x=1694647425; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=2VfrQb5e0vgI+9aUIGPfY0RfKDm+2F21N5RxQy/EsAk=; b=GvIILokqMJZFvmH0Pofaqip061CRrY0Yt+uiN0PWqVWKeAb8ce3r9LU6qcGjCXARIl lZSF1Z+/XrV2mky4CDrvp9FHXOUB0FU3n6ZgiHJ+BAXXOwKSD+RSehmVcb8fo30sHAkt VcVdWH4z3e6ZU4DYEjJklcNXEF87sV7lwXTOfkBpuHViU2cCPdgSEmNbCe18hju8PLkU MWOoMu0DftJJuwuIL3tUHJcMbjgfpxtEsGvAJODAEykWUMTRns8kwpVDuqH9LzBlLJEr On/PxeWiso52DvZ1Pe0Ys4uNPcaY1oXHfQHt3OayuACtvc7Q/tNjwDgDqHCQvwQjmrW5 h0LQ== X-Google-DKIM-Signature: v=1; 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boundary="000000000000e62d1e0604b9083b" X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000e62d1e0604b9083b Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LGTM Edwin Lu =E6=96=BC 2023=E5=B9=B49=E6=9C=887=E6=97=A5 = =E9=80=B1=E5=9B=9B 01:51 =E5=AF=AB=E9=81=93=EF=BC=9A > This patch adds types to vector instructions that were added after or were > missed by the original patch > https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html > > gcc/ChangeLog: > > * config/riscv/autovec-opt.md: Update types > * config/riscv/autovec.md: likewise > > Signed-off-by: Edwin Lu > --- > gcc/config/riscv/autovec-opt.md | 42 ++++++++++++++++++++++----------- > gcc/config/riscv/autovec.md | 28 +++++++++++++++------- > 2 files changed, 47 insertions(+), 23 deletions(-) > > diff --git a/gcc/config/riscv/autovec-opt.md > b/gcc/config/riscv/autovec-opt.md > index 1ca5ce97193..6cc1a01629c 100644 > --- a/gcc/config/riscv/autovec-opt.md > +++ b/gcc/config/riscv/autovec-opt.md > @@ -728,7 +728,8 @@ (define_insn_and_split "*cond_abs" > gen_int_mode (GET_MODE_NUNITS > (mode), Pmode), > const0_rtx)); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine vlmax neg and UNSPEC_VCOPYSIGN > (define_insn_and_split "*copysign_neg" > @@ -746,7 +747,8 @@ (define_insn_and_split "*copysign_neg" > riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (mode), > riscv_vector::BINARY_OP, operands); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine sign_extend/zero_extend(vf2) and vcond_mask > (define_insn_and_split "*cond_" > @@ -765,7 +767,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine sign_extend/zero_extend(vf4) and vcond_mask > (define_insn_and_split "*cond_" > @@ -784,7 +787,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine sign_extend/zero_extend(vf8) and vcond_mask > (define_insn_and_split "*cond_" > @@ -803,7 +807,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine trunc(vf2) + vcond_mask > (define_insn_and_split "*cond_trunc" > @@ -823,7 +828,8 @@ (define_insn_and_split > "*cond_trunc" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask > (define_insn_and_split "*cond_extend" > @@ -842,7 +848,8 @@ (define_insn_and_split > "*cond_extend" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine FP trunc(vf2) + vcond_mask > (define_insn_and_split "*cond_trunc" > @@ -862,7 +869,8 @@ (define_insn_and_split > "*cond_trunc" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(FP->INT) + vcond_mask > (define_insn_and_split "*cond_" > @@ -882,7 +890,8 @@ (define_insn_and_split "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(INT->FP) + vcond_mask > (define_insn_and_split "*cond_" > @@ -902,7 +911,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(FP->2xINT) + vcond_mask > (define_insn_and_split "*cond_" > @@ -922,7 +932,8 @@ (define_insn_and_split "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(INT->2xFP) + vcond_mask > (define_insn_and_split "*cond_" > @@ -942,7 +953,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(2xFP->INT) + vcond_mask > (define_insn_and_split "*cond_" > @@ -962,7 +974,8 @@ (define_insn_and_split "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(2xINT->FP) + vcond_mask > (define_insn_and_split "*cond_2" > @@ -982,4 +995,5 @@ (define_insn_and_split > "*cond_2" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 0f9d1fe2c8e..047a66b238f 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -558,6 +558,7 @@ (define_insn_and_split "@vcond_mask_" > riscv_vector::MERGE_OP, operands); > DONE; > } > + [(set_attr "type" "vector")] > ) > > ;; > ------------------------------------------------------------------------- > @@ -645,7 +646,8 @@ (define_insn_and_split "2" > insn_code icode =3D code_for_pred_vf4 (, mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands= ); > DONE; > -}) > +} > +[(set_attr "type" "vext")]) > > (define_insn_and_split "2" > [(set (match_operand:VOEXTI 0 "register_operand") > @@ -659,7 +661,8 @@ (define_insn_and_split "2" > insn_code icode =3D code_for_pred_vf8 (, mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands= ); > DONE; > -}) > +} > +[(set_attr "type" "vext")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [INT] Truncation > @@ -815,7 +818,8 @@ (define_insn_and_split "2" > insn_code icode =3D code_for_pred (, mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands= ); > DONE; > -}) > +} > +[(set_attr "type" "vfcvtftoi")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [FP<-INT] Conversions > @@ -837,7 +841,8 @@ (define_insn_and_split "2" > insn_code icode =3D code_for_pred (, mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, > operands); > DONE; > -}) > +} > +[(set_attr "type" "vfcvtitof")]) > > ;; > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > ;; =3D=3D Widening/narrowing Conversions > @@ -862,7 +867,8 @@ (define_insn_and_split "2" > insn_code icode =3D code_for_pred_widen (, mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands= ); > DONE; > -}) > +} > +[(set_attr "type" "vfwcvtftoi")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [FP<-INT] Widening Conversions > @@ -883,7 +889,8 @@ (define_insn_and_split "2" > insn_code icode =3D code_for_pred_widen (, mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands= ); > DONE; > -}) > +} > +[(set_attr "type" "vfwcvtitof")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [INT<-FP] Narrowing Conversions > @@ -904,7 +911,8 @@ (define_insn_and_split "2" > insn_code icode =3D code_for_pred_narrow (, mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands= ); > DONE; > -}) > +} > +[(set_attr "type" "vfncvtftoi")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [FP<-INT] Narrowing Conversions > @@ -925,7 +933,8 @@ (define_insn_and_split "2" > insn_code icode =3D code_for_pred_narrow (, mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, > operands); > DONE; > -}) > +} > +[(set_attr "type" "vfncvtitof")]) > > ;; > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > ;; =3D=3D Unary arithmetic > @@ -986,7 +995,8 @@ (define_insn_and_split "2" > insn_code icode =3D code_for_pred (, mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands= ); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; > -------------------------------------------------------------------------= ------ > ;; - [FP] Square root > -- > 2.34.1 > > --000000000000e62d1e0604b9083b--