From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by sourceware.org (Postfix) with ESMTPS id D63D5382BC39 for ; Sun, 19 Nov 2023 06:48:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D63D5382BC39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D63D5382BC39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::130 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700376537; cv=none; b=RJS4LJJkdFsDaJQe1uXwO47DYuZ9LRjtR5lKjgfNLf5RA+a7mhvX9tY/jdwuc4Gtjyx8tF24Zbmkctin3E/uJpOKtcwRBPXVM6Mz+TzS0jRKhqLa9phtol60BcmOhzIBKxRZGy1hYD1ul7vcSScg4NupZleD02js3F6UoVbQsVM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700376537; c=relaxed/simple; bh=P8LHeXLJ8W2/zg5bfI29AiXGegBHshL6EhVurfeY6IE=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=Ni20wThA2O/1uuFBfmljOlCiKOrfAzv6A3l55668/Mr91zpBPEcOyLcP3dQ/5ggwtWMb6wy8J27MYuRGxN2G8t4QJiRZSHdBS4zjjPaWGhlJzj23AgEjXdz2bCvNTWqSxCM/8hNlobeLRBuOPNqRzKtTfK5V76cs1zqAOzYQ5ws= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-507bd64814fso4722595e87.1 for ; Sat, 18 Nov 2023 22:48:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700376532; x=1700981332; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=17hmNGhn4j2MGGOyhn+X5tnhVqdjNa046YrWiexWy2k=; b=ECGTwg3+VmkZXBgyUIZebIVxFuqvoOK3gXgUEC4df+obCp9TmmeSArHuFwcHF8hGpb 2797KhjWb3J8ndb8GK8ZYcPRt+N3Y9AuZc69jB9E4JosBT9RNImQFonZ9oxCMUlOnHS8 9cpXgzv1oApGRSGbmpR0QzpOJRbEfPqtTpRAmLtCHDLErPPcZovzJBi429lp0mJgeqyt PhI0ha9NluwZQE+PiNAw3t48Rq8FyUjSrPc4hzPH89dWwCuMRAzMoaA87JWuj9OnlE4Q 3RZfNOMkWvLpMG5QQYnbySh3prAuJSqjxc2ejnozVnH6hAGWU2h0zUEmLLEhqiysIvOF fRVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700376532; x=1700981332; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=17hmNGhn4j2MGGOyhn+X5tnhVqdjNa046YrWiexWy2k=; b=rpr6Z5jTsDZtLBN19RwUrvwCiJHJVOgSpE4qBTRyu2/vkaQqJIHWfzYLrfnvvfACaQ Bh05DAQemI+coci01IgToTYTlS8pJSdNWhmk059eVICz29Dlrlda9cxG5Ja7DtauA65D KJqNqVBiEGwKp+dx7+3ubvEnKWQMvKHVmET3lQ8VPV8gb+wzoD99tSJwNapxheJCHVoC o0c4kmngCIJPZlMoAsZIA6dGDIc5M+vu3u5+rXoGhv+Z39WU8kbfKZnVchx8Ba5CBkTe EdFXP6WBxERU6mlGWurc6Z+3WBXSLQ+moW16YWmbj61xO3vlHwoywGRvMueQOUbowarY t5dQ== X-Gm-Message-State: AOJu0YzeVsFuMFmN2RFq9m5x1U36/NWijETZC2REV3+ZuDRLFXAHNcrt 4VIHG0Z/aIaTA+Wa5mKwx7gF1t69rqk39khSzGo= X-Google-Smtp-Source: AGHT+IEVy92n6Xw2PTwWXXJuGLQFgtZmaTIgL7nXhkZtxXYBuW+DRm/0qFhLulm680nyYzMib6oA42LkNzBRviN5BD8= X-Received: by 2002:ac2:5988:0:b0:500:d970:6541 with SMTP id w8-20020ac25988000000b00500d9706541mr2663218lfn.39.1700376531961; Sat, 18 Nov 2023 22:48:51 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Kito Cheng Date: Sun, 19 Nov 2023 14:48:39 +0800 Message-ID: Subject: Re: [PATCH 12/44] RISC-V/testsuite: Add branched cases for FP cond-move operations To: "Maciej W. Rozycki" Cc: gcc-patches@gcc.gnu.org, Andrew Waterman , Jim Wilson , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_ASCII_DIVIDERS,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Sun, Nov 19, 2023 at 1:38=E2=80=AFPM Maciej W. Rozycki wrote: > > Verify, for Ventana and Zicond targets and the ordered floating-point > conditional-move operations that already work as expected, that > if-conversion does *not* trigger at `-mbranch-cost=3D2' setting, which > makes original branched code sequences cheaper than their branchless > equivalents if-conversion would emit. Cover all ordered floating-point > relational operations to make sure no corner case escapes. > > gcc/testsuite/ > * gcc.target/riscv/movdibfge-ventana.c: New test. > * gcc.target/riscv/movdibfge-zicond.c: New test. > * gcc.target/riscv/movdibfgt-ventana.c: New test. > * gcc.target/riscv/movdibfgt-zicond.c: New test. > * gcc.target/riscv/movdibfle-ventana.c: New test. > * gcc.target/riscv/movdibfle-zicond.c: New test. > * gcc.target/riscv/movdibflt-ventana.c: New test. > * gcc.target/riscv/movdibflt-zicond.c: New test. > * gcc.target/riscv/movdibfne-ventana.c: New test. > * gcc.target/riscv/movdibfne-zicond.c: New test. > * gcc.target/riscv/movsibfge-ventana.c: New test. > * gcc.target/riscv/movsibfge-zicond.c: New test. > * gcc.target/riscv/movsibfgt-ventana.c: New test. > * gcc.target/riscv/movsibfgt-zicond.c: New test. > * gcc.target/riscv/movsibfle-ventana.c: New test. > * gcc.target/riscv/movsibfle-zicond.c: New test. > * gcc.target/riscv/movsibflt-ventana.c: New test. > * gcc.target/riscv/movsibflt-zicond.c: New test. > * gcc.target/riscv/movsibfne-ventana.c: New test. > * gcc.target/riscv/movsibfne-zicond.c: New test. > --- > gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c | 29 ++++++++++++++= ++++++ > gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c | 29 ++++++++++++++= ++++++ > gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c | 30 ++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c | 30 ++++++++++++++= +++++++ > 20 files changed, 598 insertions(+) > > gcc-riscv-branch-cost-test-movccf-branch.diff > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifge (double w, double x, int_t y, int_t z) > +{ > + return w >=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fge.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifge (double w, double x, int_t y, int_t z) > +{ > + return w >=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fge.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifgt (double w, double x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fgt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifgt (double w, double x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fgt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifle (double w, double x, int_t y, int_t z) > +{ > + return w <=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fle.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifle (double w, double x, int_t y, int_t z) > +{ > + return w <=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fle.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdiflt (double w, double x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + flt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdiflt (double w, double x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + flt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifne (double w, double x, int_t y, int_t z) > +{ > + return w !=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + feq.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + bne a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdifne (double w, double x, int_t y, int_t z) > +{ > + return w !=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + feq.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + bne a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifge (double w, double x, int_t y, int_t z) > +{ > + return w >=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fge.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=3Drv32gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifge (double w, double x, int_t y, int_t z) > +{ > + return w >=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fge.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifgt (double w, double x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fgt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=3Drv32gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifgt (double w, double x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fgt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifle (double w, double x, int_t y, int_t z) > +{ > + return w <=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fle.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=3Drv32gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifle (double w, double x, int_t y, int_t z) > +{ > + return w <=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + fle.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsiflt (double w, double x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + flt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=3Drv32gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsiflt (double w, double x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + flt.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + beq a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } *= / > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D2 -fdump-rtl-ce1" } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifne (double w, double x, int_t y, int_t z) > +{ > + return w !=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + feq.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + bne a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ > +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > Index: gcc/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=3Drv32gc_zicond -mtune=3Drocket -mbranch-cost=3D= 2 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsifne (double w, double x, int_t y, int_t z) > +{ > + return w !=3D x ? y : z; > +} > + > +/* Expect branched assembly like: > + > + feq.d a4,fa0,fa1 > + mv a5,a0 > + mv a0,a1 > + bne a4,zero,.L2 > + mv a0,a5 > +.L2: > + */ > + > +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+= \\." "ce1" } } */ > +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1= " } } */ > +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ > +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */