From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe36.google.com (mail-vs1-xe36.google.com [IPv6:2607:f8b0:4864:20::e36]) by sourceware.org (Postfix) with ESMTPS id 2A8843857C71 for ; Sun, 12 Feb 2023 11:34:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2A8843857C71 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe36.google.com with SMTP id h19so10312156vsv.13 for ; Sun, 12 Feb 2023 03:34:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=sM5qpRUDsaUF5gbWlk6jVRUY+6Ifu0tIoeADI2mo6KU=; b=ZyBfqYP5RIh92khNZ11sWwCB2Jl2zcqof6R6Fe2bY4qCL+bgzSLWBDztDhtwBpsURY Ae37Q13ZIEtttC1APgYlWwEx7cel8sX+Y2DwzI0It3oZXDhmfZ/dokjxcEMoZUmhdo1f QnLBKMHW7hDcFY/ajq0pxGR+qYuvGvcxVZUxxIjdvgG6viE/Aa/umZ63F8J7O/OGcsAG i+tu2ivkjDRQh05UpAFmZ0CSSmcLRuUMKGltgGSbffvaC6op6mcxJxjwjNcy213txB+u NijvgVHgZovangnDw9VKVXj23pEW6Q/COTe3Qliz1CmOvoAGXZ/DJkssnxnsRwlag0xm mhBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=sM5qpRUDsaUF5gbWlk6jVRUY+6Ifu0tIoeADI2mo6KU=; b=uQp0hCPCcSaPku7Vb0ebItsUxEzDjNpptDwg4JJFTz5UMyCZP1hijMhXqjw75JqqUY 9FnZ0I0oYxBI803Z/pg6YtPfj2BKN6cpKncGhHPb8GAJ9bSEaRnpytN8LK+Boed7+c/G iCQNLWG3sp+24/6h87jcsIRnICRqc+iQAOq0xgIfRkamHLF/ZrDH18us3KNgZhN/gJRK rVRjntw9cpfX7xBNsbl6MeMRNIoMDiqGg9caG+1j69PGRD1FUBdBADRv3qgG3q4XyywJ 7CYQGhlsFH53P4R3Fmm639IuCJoYeP53ZLHb73djci6YT2caINRGOziuAT3BYTIcFEQa h37w== X-Gm-Message-State: AO0yUKXLjwVlVIXSg3IIQU2Vh6jMD26VAFeIKBidIcN6O3SpZRdeDPZ2 F8+5i6uhvYt+aUae2149jy9sXlx+tt9TKDJf+CJuR2hq X-Google-Smtp-Source: AK7set+JqV3ripntKMIWoFFmVAktXeQ/Fl1ts8SrVmK5NMCXEr5GANRbpDKV4NmoUrtevu6V+uDVIFgRID3JTlVrypU= X-Received: by 2002:a67:e206:0:b0:3f1:cdec:49da with SMTP id g6-20020a67e206000000b003f1cdec49damr3438577vsa.52.1676201680211; Sun, 12 Feb 2023 03:34:40 -0800 (PST) MIME-Version: 1.0 References: <20230203094259.673-1-jinma@linux.alibaba.com> In-Reply-To: <20230203094259.673-1-jinma@linux.alibaba.com> From: Kito Cheng Date: Sun, 12 Feb 2023 19:34:28 +0800 Message-ID: Subject: Re: [PATCH v1] RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET. To: Jin Ma Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, palmer@dabbelt.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed, thanks :) On Fri, Feb 3, 2023 at 5:45 PM Jin Ma via Gcc-patches wrote: > > The gen_insn method is used to generate ADJUST_SP_RTX here, which has certain > potential risks: > > When the architecture adds pre-processing to `define_insn "adddi3"`, such as > `define_expend "adddi3"`, the gen_expand will be automatically called here, > causing the patern to emit directly, which will cause insn to enter REG_NOTE > for `DWARF` instead of patern. > > The following error REG_NOTE occurred: > error: invalid rtl sharing found in the insn: > (insn 19 3 20 2 (parallel [ > ... > ]) > (expr_list:REG_CFA_ADJUST_CFA > (insn 18 0 0 (set (reg/f:DI 2 sp) > (plus:DI (reg/f:DI 2 sp) > (const_int -16 [0xfffffffffffffff0]))) -1 > (nil)))) > > In fact, the correct one should be the following: > (insn 19 3 20 2 (parallel [ > ... > ]) > (expr_list:REG_CFA_ADJUST_CFA > (set (reg/f:DI 2 sp) > (plus:DI (reg/f:DI 2 sp) > (const_int -16 [0xfffffffffffffff0]))))) > > Following the treatment of arm or other architectures, it is more reasonable to > use gen_SET here. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Change gen_add3_insn > to gen_rtx_SET. > (riscv_adjust_libcall_cfi_epilogue): Likewise. > --- > gcc/config/riscv/riscv.cc | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 3b7804b7501..c9c6e53c6d0 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5054,8 +5054,9 @@ riscv_adjust_libcall_cfi_prologue () > } > > /* Debug info for adjust sp. */ > - adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, > - stack_pointer_rtx, GEN_INT (-saved_size)); > + adjust_sp_rtx = > + gen_rtx_SET (stack_pointer_rtx, > + gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, GEN_INT (-saved_size))); > dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, > dwarf); > return dwarf; > @@ -5176,8 +5177,9 @@ riscv_adjust_libcall_cfi_epilogue () > int saved_size = cfun->machine->frame.save_libcall_adjustment; > > /* Debug info for adjust sp. */ > - adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, > - stack_pointer_rtx, GEN_INT (saved_size)); > + adjust_sp_rtx = > + gen_rtx_SET (stack_pointer_rtx, > + gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, GEN_INT (saved_size))); > dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, > dwarf); > > -- > 2.17.1 >