From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2b.google.com (mail-vs1-xe2b.google.com [IPv6:2607:f8b0:4864:20::e2b]) by sourceware.org (Postfix) with ESMTPS id E91F53858C53 for ; Thu, 24 Aug 2023 14:24:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E91F53858C53 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2b.google.com with SMTP id ada2fe7eead31-44d3b9bc4c3so595735137.0 for ; Thu, 24 Aug 2023 07:24:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692887075; x=1693491875; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=oLTaUXhWSEQNZ0KopexYwbWNvE6KRuYdYbnUCivIeQk=; b=HPoUGGEjy8BjEzzHMWC/NOZeOOtVp0IXBpbQNcxB0Y9LIN3NBiMZaskQyHMh2F18jB bA/KqEnIA4tnQC3FNvZYm1ddpc9mdGXjQGClXbv2pO5hbHniDP3Z6qqjX3+sa5Pnas73 wjsh8C6UMAsebRgYOGz23oCAy/crfcq+rjhCcCxQ3lVO5mACeE+rnS8JwdmsDQcXdD17 CPunOeLq3GY24BTsSmC/UC8VjKXnc+sHCMKU90/BAMNaH2/L5ccqsqq5LeldA6PdkQ7u hIZXIgWukBn8RS3iX0Mrrh+VvXaS4dPYGp6tJpueLg9uXndhY5eUL2y3ojuBZY0CyzBO ZI4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692887075; x=1693491875; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oLTaUXhWSEQNZ0KopexYwbWNvE6KRuYdYbnUCivIeQk=; b=dCeOxJbIhWrGbeoI8qD4CWGnSIa0Btm3knx8Y4dbl1IaK9kF/QCZESWNGezpuQkzeP OqzrWkkpVeZKW/u4tdvpePtZ3gBm22Y5lvwBhxfg/cHigfHqe6lYenr/EMlh0OmVkioV PCtYlQ03GgaVRqjlQqYPeimmVs/A6DmQ6F2AOiHe5a1FRkcBdpgH3xUnxO6JEN5YkKcp GQ70vn6AkE7+QT6RjdkjOucWl0J71YAO5r2tFL5BjzTnzCAQtsmMZ9oUvR9LOyYjxJjG iaiCReBmpZ9sQ/o6qhcaZ0hRatkQs+97GrDC+4/deK3/UuLVPm9hsAPn48AADtcQwGLL esRw== X-Gm-Message-State: AOJu0YzgGM6O0A9KgFWmE1FMlKcz7PX4tuVWOu2Sbq5kCdlLm/iG4q7y YAHVgHUMtxAE6taeO9BMGdcqejktZA1696BBLCM= X-Google-Smtp-Source: AGHT+IG9PCpeZwF1dY15YxQltB1+j6XRHci4dY31YF0CoFGJnZwyJiwo9v5nnSbvE8shbJtvSjn1YYOkf6jXmD8cE9Y= X-Received: by 2002:a05:6102:533:b0:44d:42c4:f4bf with SMTP id m19-20020a056102053300b0044d42c4f4bfmr6634243vsa.10.1692887074980; Thu, 24 Aug 2023 07:24:34 -0700 (PDT) MIME-Version: 1.0 References: <20230824093446.651760-1-pan2.li@intel.com> In-Reply-To: <20230824093446.651760-1-pan2.li@intel.com> From: Kito Cheng Date: Thu, 24 Aug 2023 22:24:23 +0800 Message-ID: Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovec To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, yanzhang.wang@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Thu, Aug 24, 2023 at 5:35=E2=80=AFPM Pan Li via Gcc-patches wrote: > > From: Pan Li > > There will be a case like below for intrinsic and autovec combination. > > vfadd RTZ <- intrinisc static rounding > vfnmsub <- autovec/autovec-opt > > The autovec generated vfnmsub should take DYN mode, and the > frm must be restored before the vfnmsub insn. This patch > would like to fix this issue by: > > * Add the frm operand to the autovec/autovec-opt pattern. > * Set the frm_mode attr to DYN. > > Thus, the frm flow when combine autovec and intrinsic should be. > > +------------ > | frrm a5 > | ... > | fsrmi 4 > | vfadd <- intrinsic static rounding. > | ... > | fsrm a5 > | vfnmsub <- autovec/autovec-opt > | ... > +------------ > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmsac/vfnmsub > * config/riscv/autovec.md: Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: New test= . > --- > gcc/config/riscv/autovec-opt.md | 34 ++++--- > gcc/config/riscv/autovec.md | 30 ++++--- > .../rvv/base/float-point-frm-autovec-3.c | 88 +++++++++++++++++++ > 3 files changed, 126 insertions(+), 26 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-f= rm-autovec-3.c > > diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-o= pt.md > index 732a51edacd..54ca6df721c 100644 > --- a/gcc/config/riscv/autovec-opt.md > +++ b/gcc/config/riscv/autovec-opt.md > @@ -523,13 +523,15 @@ (define_insn_and_split "*single_widen_fma" > ;; vect__13.182_33 =3D .FNMA (vect__11.180_35, vect__8.176_40, vect__4.1= 72_45); > (define_insn_and_split "*double_widen_fnma" > [(set (match_operand:VWEXTF 0 "register_operand") > - (fma:VWEXTF > - (neg:VWEXTF > + (unspec:VWEXTF > + [(fma:VWEXTF > + (neg:VWEXTF > + (float_extend:VWEXTF > + (match_operand: 2 "register_operand"))) > (float_extend:VWEXTF > - (match_operand: 2 "register_operand"))) > - (float_extend:VWEXTF > - (match_operand: 3 "register_operand")) > - (match_operand:VWEXTF 1 "register_operand")))] > + (match_operand: 3 "register_operand")) > + (match_operand:VWEXTF 1 "register_operand")) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > @@ -540,17 +542,20 @@ (define_insn_and_split "*double_widen_fnma" > DONE; > } > [(set_attr "type" "vfwmuladd") > - (set_attr "mode" "")]) > + (set_attr "mode" "") > + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > ;; This helps to match ext + fnma. > (define_insn_and_split "*single_widen_fnma" > [(set (match_operand:VWEXTF 0 "register_operand") > - (fma:VWEXTF > - (neg:VWEXTF > - (float_extend:VWEXTF > - (match_operand: 2 "register_operand"))) > - (match_operand:VWEXTF 3 "register_operand") > - (match_operand:VWEXTF 1 "register_operand")))] > + (unspec:VWEXTF > + [(fma:VWEXTF > + (neg:VWEXTF > + (float_extend:VWEXTF > + (match_operand: 2 "register_operand"))) > + (match_operand:VWEXTF 3 "register_operand") > + (match_operand:VWEXTF 1 "register_operand")) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > @@ -567,7 +572,8 @@ (define_insn_and_split "*single_widen_fnma" > DONE; > } > [(set_attr "type" "vfwmuladd") > - (set_attr "mode" "")]) > + (set_attr "mode" "") > + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > ;; ---------------------------------------------------------------------= ---- > ;; ---- [FP] VFWMSAC > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 0c1c546817a..28396c6175d 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -1174,24 +1174,29 @@ (define_insn_and_split "*fma" > (define_expand "fnma4" > [(parallel > [(set (match_operand:VF 0 "register_operand") > - (fma:VF > - (neg:VF > - (match_operand:VF 1 "register_operand")) > - (match_operand:VF 2 "register_operand") > - (match_operand:VF 3 "register_operand"))) > + (unspec:VF > + [(fma:VF > + (neg:VF > + (match_operand:VF 1 "register_operand")) > + (match_operand:VF 2 "register_operand") > + (match_operand:VF 3 "register_operand")) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) > (clobber (match_dup 4))])] > "TARGET_VECTOR" > { > operands[4] =3D gen_reg_rtx (Pmode); > - }) > + } > + [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > (define_insn_and_split "*fnma" > [(set (match_operand:VF 0 "register_operand" "=3Dvr, vr, ?&vr") > - (fma:VF > - (neg:VF > - (match_operand:VF 1 "register_operand" " %0, vr, vr")) > - (match_operand:VF 2 "register_operand" " vr, vr, vr") > - (match_operand:VF 3 "register_operand" " vr, 0, vr"))) > + (unspec:VF > + [(fma:VF > + (neg:VF > + (match_operand:VF 1 "register_operand" " %0, vr, vr")) > + (match_operand:VF 2 "register_operand" " vr, vr, vr") > + (match_operand:VF 3 "register_operand" " vr, 0, vr")) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) > (clobber (match_operand:P 4 "register_operand" "=3Dr,r,r"))] > "TARGET_VECTOR" > "#" > @@ -1205,7 +1210,8 @@ (define_insn_and_split "*fnma" > DONE; > } > [(set_attr "type" "vfmuladd") > - (set_attr "mode" "")]) > + (set_attr "mode" "") > + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > ;; ---------------------------------------------------------------------= ---- > ;; ---- [FP] VFMSAC and VFMSUB > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-auto= vec-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3= .c > new file mode 100644 > index 00000000000..abedfc1b8fb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c > @@ -0,0 +1,88 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv --param=3Driscv-autovec-preference=3Df= ixed-vlmax -ffast-math -mabi=3Dlp64 -O3 -Wno-psabi" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "riscv_vector.h" > + > +/* > +**test_1: > +** ... > +** frrm\t[axt][0-9]+ > +** ... > +** fsrmi\t1 > +** ... > +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** vfnmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** ret > +*/ > +void > +test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t= vl, > + double *in1, double *in2, double *out) > +{ > + *op_out =3D __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl); > + > + for (int i =3D 0; i < vl; ++i) > + out[i] =3D - in1[i] * in2[i] + out[i]; > +} > + > +/* > +**test_2: > +** ... > +** frrm\t[axt][0-9]+ > +** ... > +** fsrmi\t1 > +** ... > +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** vfnmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrmi\t4 > +** ... > +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** ret > +*/ > +void > +test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t= vl, > + double *in1, double *in2, double *out) > +{ > + op2 =3D __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl); > + > + for (int i =3D 0; i < vl; ++i) > + out[i] =3D - out[i] * in1[i] + in2[i]; > + > + *op_out =3D __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl); > +} > + > +/* > +**test_3: > +** ... > +** frrm\t[axt][0-9]+ > +** ... > +** vfnmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrmi\t4 > +** ... > +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** ret > +*/ > +void > +test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t= vl, > + double *in1, double *in2, double *in3, double *out) > +{ > + for (int i =3D 0; i < vl; ++i) > + out[i] =3D - in2[i] * out[i] + in1[i]; > + > + *op_out =3D __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl); > +} > -- > 2.34.1 >