From: Kito Cheng <kito.cheng@gmail.com>
To: Lehua Ding <lehua.ding@rivai.ai>
Cc: Jeff Law <jeffreyalaw@gmail.com>,
gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai
Subject: Re: [PATCH] RISC-V: Add conditional sqrt autovec pattern
Date: Wed, 6 Sep 2023 16:17:50 +0800 [thread overview]
Message-ID: <CA+yXCZD52_h1COhP_U1iV+1ErnbvnX3pX5G8O4ep0Lm=CY268Q@mail.gmail.com> (raw)
In-Reply-To: <6892DD6296999D2D+3ea5b1b3-be76-46ce-8a6c-bae6fc9e06f6@rivai.ai>
Got failed on the trunk, could you take a look?
=== gcc: Unexpected fails for rv32imafdc ilp32d medlow ===
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
=== gcc: Unexpected fails for rv64imac lp64 medlow ===
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
=== gcc: Unexpected fails for rv64imafdc lp64d medlow ===
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
========= Summary of gcc testsuite =========
| # of unexpected case / # of unique unexpected case
| gcc | g++ | gfortran |
rv32imac/ ilp32/ medlow | 0 / 0 | 0 / 0 | 0 / 0 |
rv32imafdc/ ilp32d/ medlow | 32 / 2 | 0 / 0 | 0 / 0 |
rv64imac/ lp64/ medlow | 32 / 2 | 0 / 0 | 0 / 0 |
rv64imafdc/ lp64d/ medlow | 32 / 2 | 0 / 0 | 0 / 0 |
On Wed, Sep 6, 2023 at 12:14 PM Lehua Ding <lehua.ding@rivai.ai> wrote:
>
>
>
> On 2023/9/6 8:31, Jeff Law wrote:
> >
> >
> > On 9/3/23 22:49, Lehua Ding wrote:
> >> This patch adds a combined pattern for combining vfsqrt.v and vcond_mask.
> >>
> >> gcc/ChangeLog:
> >>
> >> * config/riscv/autovec-opt.md (*cond_<optab><mode>):
> >> Add sqrt + vcond_mask combine pattern.
> >> * config/riscv/autovec.md (<optab><mode>2):
> >> Change define_expand to define_insn_and_split.
> >>
> >> gcc/testsuite/ChangeLog:
> >>
> >> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: New test.
> >> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: New test.
> >> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: New test.
> >> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: New test.
> > OK. Thanks.
> >
> > FWIW, I thought we only had the reciprocal sqrt estimator, but in fact
> > rvv does define a real vector sqrt. So the concerns we kicked around
> > in the meeting this morning turned out not be warranted.
> >
> > This raises one of the very interesting questions in this space,
> > specifically whether or not we should be using the rsqrt estimator with
> > correction steps. Unless the vfsqrt latency is really bad, it's going
> > to be hard to make a vfrsqrt7 based sequence faster -- but the vfrsqrt7
> > sequences will be pipelinable while vfsqrt almost certainly isn't.
> >
> > Sadly we don't have a scalar FP rsqrt estimator. Though I certainly
> > ponder using the vector one -- there's a neat trick you can do with the
> > nab benchmark from spec and produce sqrt and rsqrt at the same time with
> > a Goldschmidt sequence. It requires a bit of hackery to make new tree
> > nodes, but it was definitely worth it on other targets I've worked on.
>
> Committed, thank Jeff.
>
> --
> Best,
> Lehua
>
next prev parent reply other threads:[~2023-09-06 8:18 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-04 4:49 Lehua Ding
2023-09-06 0:31 ` Jeff Law
2023-09-06 4:13 ` Lehua Ding
2023-09-06 8:17 ` Kito Cheng [this message]
2023-09-06 8:22 ` Lehua Ding
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