From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa2d.google.com (mail-vk1-xa2d.google.com [IPv6:2607:f8b0:4864:20::a2d]) by sourceware.org (Postfix) with ESMTPS id 367843858D32 for ; Wed, 6 Sep 2023 08:18:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 367843858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa2d.google.com with SMTP id 71dfb90a1353d-49351972caeso546905e0c.1 for ; Wed, 06 Sep 2023 01:18:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693988281; x=1694593081; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=KTGRqkor9Gs0RaOT2fklVObhsFGtoqT+Iv9vu1aXGRE=; b=FaM1zzUZUazFr27kuoYcnaf0ZL5W5YjjeKb0NZi+SQAMRh2IOESHJUK7xi3zm68vNH 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AOJu0YzaRbCFLKtZygm8zo0T1avY20HgQD2BKFk8wbzTI8tQf3Oy1o5W 5qMyvLbfRXx74QL6mi8K5hqxcxbQPOzB2xroeKKQ7EJaWL4= X-Google-Smtp-Source: AGHT+IGXoaHNBuD5Km8KDIboSKz28E349sn3Rr0lBdxvznyAJ14dHB5zGkxjIH7KcLlPBuGH5tSH8uqkyhgAkSfKWpY= X-Received: by 2002:a67:fb55:0:b0:44d:5435:a3e with SMTP id e21-20020a67fb55000000b0044d54350a3emr2074320vsr.9.1693988281131; Wed, 06 Sep 2023 01:18:01 -0700 (PDT) MIME-Version: 1.0 References: <20230904044906.2546875-1-lehua.ding@rivai.ai> <6892DD6296999D2D+3ea5b1b3-be76-46ce-8a6c-bae6fc9e06f6@rivai.ai> In-Reply-To: <6892DD6296999D2D+3ea5b1b3-be76-46ce-8a6c-bae6fc9e06f6@rivai.ai> From: Kito Cheng Date: Wed, 6 Sep 2023 16:17:50 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add conditional sqrt autovec pattern To: Lehua Ding Cc: Jeff Law , gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Got failed on the trunk, could you take a look? =3D=3D=3D gcc: Unexpected fails for rv32imafdc ilp32d medlo= w =3D=3D=3D FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 =3D=3D=3D gcc: Unexpected fails for rv64imac lp64 medlow =3D= =3D=3D FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 =3D=3D=3D gcc: Unexpected fails for rv64imafdc lp64d medlow = =3D=3D=3D FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler \\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3 =3D=3D=3D=3D=3D=3D=3D=3D=3D Summary of gcc testsuite =3D=3D= =3D=3D=3D=3D=3D=3D=3D | # of unexpected case / # of unique unexpected = case | gcc | g++ | gfortran | rv32imac/ ilp32/ medlow | 0 / 0 | 0 / 0 | 0 / 0 | rv32imafdc/ ilp32d/ medlow | 32 / 2 | 0 / 0 | 0 / 0 | rv64imac/ lp64/ medlow | 32 / 2 | 0 / 0 | 0 / 0 | rv64imafdc/ lp64d/ medlow | 32 / 2 | 0 / 0 | 0 / 0 | On Wed, Sep 6, 2023 at 12:14=E2=80=AFPM Lehua Ding wr= ote: > > > > On 2023/9/6 8:31, Jeff Law wrote: > > > > > > On 9/3/23 22:49, Lehua Ding wrote: > >> This patch adds a combined pattern for combining vfsqrt.v and vcond_ma= sk. > >> > >> gcc/ChangeLog: > >> > >> * config/riscv/autovec-opt.md (*cond_): > >> Add sqrt + vcond_mask combine pattern. > >> * config/riscv/autovec.md (2): > >> Change define_expand to define_insn_and_split. > >> > >> gcc/testsuite/ChangeLog: > >> > >> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: New test. > >> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: New test. > >> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: New test. > >> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: New test. > > OK. Thanks. > > > > FWIW, I thought we only had the reciprocal sqrt estimator, but in fact > > rvv does define a real vector sqrt. So the concerns we kicked around > > in the meeting this morning turned out not be warranted. > > > > This raises one of the very interesting questions in this space, > > specifically whether or not we should be using the rsqrt estimator with > > correction steps. Unless the vfsqrt latency is really bad, it's going > > to be hard to make a vfrsqrt7 based sequence faster -- but the vfrsqrt7 > > sequences will be pipelinable while vfsqrt almost certainly isn't. > > > > Sadly we don't have a scalar FP rsqrt estimator. Though I certainly > > ponder using the vector one -- there's a neat trick you can do with the > > nab benchmark from spec and produce sqrt and rsqrt at the same time wit= h > > a Goldschmidt sequence. It requires a bit of hackery to make new tree > > nodes, but it was definitely worth it on other targets I've worked on. > > Committed, thank Jeff. > > -- > Best, > Lehua >