From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x934.google.com (mail-ua1-x934.google.com [IPv6:2607:f8b0:4864:20::934]) by sourceware.org (Postfix) with ESMTPS id C48733858D33 for ; Thu, 20 Apr 2023 02:26:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C48733858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x934.google.com with SMTP id x8so1208526uau.9 for ; Wed, 19 Apr 2023 19:26:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681957599; x=1684549599; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=QOHGGFyA+m+5KP65AzD06Ezpp3h0Z4R+2Kp3GwyYm9M=; b=o2IdYo2FTylv+YLV58Jr/M55DjeHtOJ+BnJsxBXLkFHDYWB98pSiOeJv9uOLgei7Q9 XvvzEuFRYohYTeecbPqGkHC2AuVMfyYkp41daPjhsZL4QGk1LUHPDg5MuinfbciNhOew eoR41sXWU0HpXP/VvS9VXLvs9QlZ0NHEEMlK2WhrqPY9iIYsqN5eaiuvr1YQaKSLbnZd oF64wU2ipzEhM53h/bPupHHYO3GP76SlZS9oNjy7sKLIE0bDdr3bHunME+t2iol23O9A 85nzHyuOg2jt9N5U6SOrc82A10RrtdJcAC8eSdyIb79sMKKuOxdSyNAg9RQyG8VPQ+Lr KS0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681957599; x=1684549599; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=QOHGGFyA+m+5KP65AzD06Ezpp3h0Z4R+2Kp3GwyYm9M=; b=S1coNs0jPcNz41rUyLDmwieLlnh2HfVMI5bnqTOoxzBQRlm1HQu4ELPswRxwzkNpHR UaeDL4XvVGnmiB1FJuyGcAHKiRxw2lwJ/CLz4yiCXq7jX+zezdo/Hm3xhUPYYQM8kdgG IRuCKmAT7751PGv4EgzDPdcjUvLdjNfUagfRlOxF90dSfS4m/N6CUSO5XVZ3C7YWNqNs keSfHjV10GXQfcL0v06KNEyX/5M/sS9jYL8Rn2WypdY/O4Vp9kAECJ6Ry2F7QlW72/cY DtZloSnOROvVNvwL4AocSawlycx8l6viVg/PyxC19aMFVqSmC1AfmKDBJ4sSLdzldnNS RcjA== X-Gm-Message-State: AAQBX9cNl3vHnMru6YyBo+NbNh2yQ42F5LbyrlguEA47/7GhExE1ty1B QNwG7HafnElMsIOmTNQnfkD8bGgRXwcM6MD1zOE= X-Google-Smtp-Source: AKy350aueA9fP/eawfOnQfLIbunPdZaDssDys+3UnqvokocpCLtcZ2BNwp5zbwIhDcKnzSVnHpSocBimjvVk8OrlKaM= X-Received: by 2002:a1f:d907:0:b0:440:4920:e620 with SMTP id q7-20020a1fd907000000b004404920e620mr149644vkg.4.1681957598942; Wed, 19 Apr 2023 19:26:38 -0700 (PDT) MIME-Version: 1.0 References: <20230419164214.1032017-1-juzhe.zhong@rivai.ai> <20230419164214.1032017-3-juzhe.zhong@rivai.ai> In-Reply-To: <20230419164214.1032017-3-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Thu, 20 Apr 2023 10:26:27 +0800 Message-ID: Subject: Re: [PATCH 2/3 V2] RISC-V: Enable basic auto-vectorization for RVV To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com, jeffreyalaw@gmail.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > +/* Return the vectorization machine mode for RVV according to LMUL. */ > +machine_mode > +preferred_simd_mode (scalar_mode mode) > +{ > + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 > + which is -march=rv64gcv. Since GCC loop vectorizer report ICE > + when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. > + in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have > + VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are > + enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to > + use them. Currently, we can support auto-vectorization in > + -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or > + -march=rv32_zve32x_zvl64b are disabled. > + */ The comment above might not sync with your implementation? > + if (autovec_use_vlmax_p ()) > + { > + /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2 > + auto-vectorization since Loop Vectorizer may use VNx1SImode or > + VNx1DImode to vectorize which will create ICE in the > + 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. */ > + if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2) > + return word_mode; Actually, you've allowed TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2 > + /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and > + riscv_autovec_lmul as multiply factor to calculate the the NUNITS to > + get the auto-vectorization mode. */ > + poly_uint64 nunits; > + poly_uint64 vector_size > + = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); > + poly_uint64 scalar_size = GET_MODE_SIZE (mode); > + if (!multiple_p (vector_size, scalar_size, &nunits)) > + return word_mode; Could you put a gcc_unreachable or assertion here? I assume this should never false? if (!multiple_p (vector_size, scalar_size, &nunits)) { gcc_unreachable (); return word_mode; } > + machine_mode rvv_mode; > + if (get_vector_mode (mode, nunits).exists (&rvv_mode)) > + return rvv_mode; > + } > + /* TODO: We will support minimum length VLS auto-vectorization in the future. > + */ > + return word_mode; > +} > + > + > } // namespace riscv_vector > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 5d2550871c7..c601389b540 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -6228,7 +6228,15 @@ riscv_convert_vector_bits (void) > to set RVV mode size. The RVV machine modes size are run-time constant if > TARGET_VECTOR is enabled. The RVV machine modes size remains default > compile-time constant if TARGET_VECTOR is disabled. */ > - return TARGET_VECTOR ? poly_uint16 (1, 1) : 1; > + if (TARGET_VECTOR) > + { > + if (riscv_autovec_preference == RVV_FIXED_VLMAX) > + return (int) TARGET_MIN_VLEN / (riscv_bytes_per_vector_chunk * 8); I realized this will also effect intrinsic stuffs. So I would prefer to drop RVV_FIXED_VLMAX stuffs at this moment. e.g. $ riscv64-unknown-linux-gnu-gcc --param=riscv-autovec-preference=fixed-vlmax gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c -O2 -march=rv64gcv -S ../riscv-gnu-toolchain-trunk/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c: In function 'stach_check_alloca_1': ../riscv-gnu-toolchain-trunk/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c:41:1: error: insn does not satisfy its constraints: 41 | } | ^ (insn 37 26 40 2 (set (reg:VNx8QI 120 v24 [orig:158 data ] [158]) (reg:VNx8QI 10 a0 [ data ])) "../riscv-gnu-toolchain-trunk/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c":28:1 727 {*movvnx8qi_whole} (nil)) during RTL pass: reload ../riscv-gnu-toolchain-trunk/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c:41:1: internal compiler error: in extract_constrain_insn, at recog.cc:2692