From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa34.google.com (mail-vk1-xa34.google.com [IPv6:2607:f8b0:4864:20::a34]) by sourceware.org (Postfix) with ESMTPS id DC4423858407 for ; Fri, 3 Feb 2023 07:16:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC4423858407 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa34.google.com with SMTP id bs10so2147972vkb.3 for ; Thu, 02 Feb 2023 23:16:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=5ZBglbTgzVkEPlLnx9vm54YwW02+saM6oBv3+xECw9Q=; b=FXCpu7/kcq1Ttg4Bxr1rq6vcnGagyy1vIrBYoMkRunxvZgmwnRZdCHeJt4MwnAAgbX 8Dsh4gRYH9bEvmBu7aC4JyV2+ab9nldm9iuzkTQ0sOxR+zAn/sFNKivh+tG3YKYxxQRJ bxNkCakxkIS9KlSGCe5S1VGVyS91p/a8wf13CEJM0pWe4oxbH6dsHPnLuklngf0Y5jBj qIeWoVueTqFuZo8iGPoRSwDA6PdzmxO9FnudRzgQ+yWMUh1kE63r3mor7BCC/Ss5LyHX KmEofku+3eMp2fb3Gxy7CM6OKEFT7n3MHGv4WTykpqovWGCyOLIxzy5Ln/1scHIlr1IW 4Lwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5ZBglbTgzVkEPlLnx9vm54YwW02+saM6oBv3+xECw9Q=; b=e9cNhymZIQ+QC9zqvVL1mrzRoZd01kAsvTBaWR6GyU57BNkeDa4hQXhRHrXbjMR+hr hrnItoL3EiYauSxUld19cbu3ScRL1PFU61Ivudyc2Si5fO/OIQ4+zvUuKkYRlg2Jcec2 dJd/a4JzKQNxsBPw/poFIpe7S58ZKYTTeupw5dhjHDGODEU6zbnb45XmncUn7kckWotB D+r6WnpbpPBgNCyKBW9/5OOm67mp0xoo/f/XrSHdfWzb1DTbryWhqQ9foBwnmQLvJP2F ls6xnFGh9ODA3ORPflRMIb4RHKT/pCOrTIW9vdkI3mTQuA9fOqqowfjJXxeg6O5BSMMI I4Ow== X-Gm-Message-State: AO0yUKW/ZfzPkuPBj1PaN8qyXpCrm4WBs3HVt8Va4ZY3H9lKGienrGkU k/MA67cry2gu07WcEeFl+H6GhGSzHnF8leuA250= X-Google-Smtp-Source: AK7set/0xhGUHnnjDjc2QxrlK/BgLZptMjh531yxt0mEGRDlbWAg5e2u4COuzwwExiGuT085Lq6D2HxrQkrd2UwVtdk= X-Received: by 2002:a05:6122:10e3:b0:3ea:40aa:5c01 with SMTP id m3-20020a05612210e300b003ea40aa5c01mr1295683vko.36.1675408597927; Thu, 02 Feb 2023 23:16:37 -0800 (PST) MIME-Version: 1.0 References: <20230131221110.20996-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230131221110.20996-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Fri, 3 Feb 2023 15:16:25 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add vsra.vx C API tests To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: committed, thanks! On Wed, Feb 1, 2023 at 6:11 AM wrote: > > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/vsra_vx-1.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx-2.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx-3.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_m-1.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_m-2.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_m-3.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_mu-1.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_mu-2.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_mu-3.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_tu-1.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_tu-2.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_tu-3.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_tum-1.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_tum-2.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_tum-3.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c: New test. > * gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c: New test. > > --- > .../gcc.target/riscv/rvv/base/vsra_vx-1.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx-2.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx-3.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_m-1.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_m-2.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_m-3.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_mu-1.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_mu-2.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_mu-3.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_tu-1.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_tu-2.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_tu-3.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_tum-1.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_tum-2.c | 160 ++++++++++++++++++ > .../gcc.target/riscv/rvv/base/vsra_vx_tum-3.c | 160 ++++++++++++++++++ > .../riscv/rvv/base/vsra_vx_tumu-1.c | 160 ++++++++++++++++++ > .../riscv/rvv/base/vsra_vx_tumu-2.c | 160 ++++++++++++++++++ > .../riscv/rvv/base/vsra_vx_tumu-3.c | 160 ++++++++++++++++++ > 18 files changed, 2880 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c > new file mode 100644 > index 00000000000..7a7a5a1a933 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8(op1,shift,vl); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4(op1,shift,vl); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2(op1,shift,vl); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1(op1,shift,vl); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2(op1,shift,vl); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4(vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4(op1,shift,vl); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8(vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8(op1,shift,vl); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4(vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4(op1,shift,vl); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2(vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2(op1,shift,vl); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1(vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1(op1,shift,vl); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2(vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2(op1,shift,vl); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4(vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4(op1,shift,vl); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8(vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8(op1,shift,vl); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2(vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2(op1,shift,vl); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1(vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1(op1,shift,vl); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2(vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2(op1,shift,vl); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4(vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4(op1,shift,vl); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8(vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8(op1,shift,vl); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1(vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1(op1,shift,vl); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2(vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2(op1,shift,vl); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4(vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4(op1,shift,vl); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8(vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8(op1,shift,vl); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c > new file mode 100644 > index 00000000000..d9d8381297f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8(op1,shift,31); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4(op1,shift,31); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2(op1,shift,31); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1(op1,shift,31); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2(op1,shift,31); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4(vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4(op1,shift,31); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8(vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8(op1,shift,31); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4(vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4(op1,shift,31); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2(vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2(op1,shift,31); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1(vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1(op1,shift,31); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2(vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2(op1,shift,31); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4(vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4(op1,shift,31); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8(vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8(op1,shift,31); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2(vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2(op1,shift,31); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1(vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1(op1,shift,31); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2(vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2(op1,shift,31); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4(vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4(op1,shift,31); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8(vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8(op1,shift,31); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1(vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1(op1,shift,31); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2(vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2(op1,shift,31); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4(vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4(op1,shift,31); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8(vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8(op1,shift,31); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c > new file mode 100644 > index 00000000000..543b4502686 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8(op1,shift,32); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4(op1,shift,32); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2(op1,shift,32); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1(op1,shift,32); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2(op1,shift,32); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4(vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4(op1,shift,32); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8(vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8(op1,shift,32); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4(vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4(op1,shift,32); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2(vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2(op1,shift,32); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1(vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1(op1,shift,32); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2(vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2(op1,shift,32); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4(vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4(op1,shift,32); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8(vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8(op1,shift,32); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2(vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2(op1,shift,32); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1(vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1(op1,shift,32); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2(vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2(op1,shift,32); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4(vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4(op1,shift,32); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8(vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8(op1,shift,32); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1(vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1(op1,shift,32); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2(vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2(op1,shift,32); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4(vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4(op1,shift,32); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8(vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8(op1,shift,32); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c > new file mode 100644 > index 00000000000..bab2ec44f2b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_m(mask,op1,shift,vl); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_m(mask,op1,shift,vl); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_m(mask,op1,shift,vl); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_m(mask,op1,shift,vl); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_m(mask,op1,shift,vl); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_m(mask,op1,shift,vl); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_m(mask,op1,shift,vl); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_m(mask,op1,shift,vl); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_m(mask,op1,shift,vl); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_m(mask,op1,shift,vl); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_m(mask,op1,shift,vl); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_m(mask,op1,shift,vl); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_m(mask,op1,shift,vl); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_m(mask,op1,shift,vl); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_m(mask,op1,shift,vl); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_m(mask,op1,shift,vl); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_m(mask,op1,shift,vl); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_m(mask,op1,shift,vl); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_m(mask,op1,shift,vl); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_m(mask,op1,shift,vl); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_m(mask,op1,shift,vl); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_m(mask,op1,shift,vl); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c > new file mode 100644 > index 00000000000..bb5c9f93798 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_m(mask,op1,shift,31); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_m(mask,op1,shift,31); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_m(mask,op1,shift,31); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_m(mask,op1,shift,31); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_m(mask,op1,shift,31); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_m(mask,op1,shift,31); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_m(mask,op1,shift,31); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_m(mask,op1,shift,31); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_m(mask,op1,shift,31); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_m(mask,op1,shift,31); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_m(mask,op1,shift,31); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_m(mask,op1,shift,31); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_m(mask,op1,shift,31); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_m(mask,op1,shift,31); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_m(mask,op1,shift,31); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_m(mask,op1,shift,31); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_m(mask,op1,shift,31); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_m(mask,op1,shift,31); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_m(mask,op1,shift,31); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_m(mask,op1,shift,31); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_m(mask,op1,shift,31); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_m(mask,op1,shift,31); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c > new file mode 100644 > index 00000000000..1d088c5021b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_m(mask,op1,shift,32); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_m(mask,op1,shift,32); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_m(mask,op1,shift,32); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_m(mask,op1,shift,32); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_m(mask,op1,shift,32); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_m(mask,op1,shift,32); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_m(mask,op1,shift,32); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_m(mask,op1,shift,32); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_m(mask,op1,shift,32); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_m(mask,op1,shift,32); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_m(mask,op1,shift,32); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_m(mask,op1,shift,32); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_m(mask,op1,shift,32); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_m(mask,op1,shift,32); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_m(mask,op1,shift,32); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_m(mask,op1,shift,32); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_m(mask,op1,shift,32); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_m(mask,op1,shift,32); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_m(mask,op1,shift,32); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_m(mask,op1,shift,32); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_m(mask,op1,shift,32); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_m(mask,op1,shift,32); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c > new file mode 100644 > index 00000000000..2885dc57793 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_mu(mask,merge,op1,shift,vl); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_mu(mask,merge,op1,shift,vl); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c > new file mode 100644 > index 00000000000..467a513587f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_mu(mask,merge,op1,shift,31); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_mu(mask,merge,op1,shift,31); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_mu(mask,merge,op1,shift,31); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_mu(mask,merge,op1,shift,31); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_mu(mask,merge,op1,shift,31); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_mu(mask,merge,op1,shift,31); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_mu(mask,merge,op1,shift,31); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_mu(mask,merge,op1,shift,31); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_mu(mask,merge,op1,shift,31); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_mu(mask,merge,op1,shift,31); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_mu(mask,merge,op1,shift,31); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_mu(mask,merge,op1,shift,31); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_mu(mask,merge,op1,shift,31); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_mu(mask,merge,op1,shift,31); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_mu(mask,merge,op1,shift,31); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_mu(mask,merge,op1,shift,31); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_mu(mask,merge,op1,shift,31); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_mu(mask,merge,op1,shift,31); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_mu(mask,merge,op1,shift,31); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_mu(mask,merge,op1,shift,31); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_mu(mask,merge,op1,shift,31); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_mu(mask,merge,op1,shift,31); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c > new file mode 100644 > index 00000000000..ca8882a3ef4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_mu(mask,merge,op1,shift,32); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_mu(mask,merge,op1,shift,32); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_mu(mask,merge,op1,shift,32); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_mu(mask,merge,op1,shift,32); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_mu(mask,merge,op1,shift,32); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_mu(mask,merge,op1,shift,32); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_mu(mask,merge,op1,shift,32); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_mu(mask,merge,op1,shift,32); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_mu(mask,merge,op1,shift,32); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_mu(mask,merge,op1,shift,32); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_mu(mask,merge,op1,shift,32); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_mu(mask,merge,op1,shift,32); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_mu(mask,merge,op1,shift,32); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_mu(mask,merge,op1,shift,32); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_mu(mask,merge,op1,shift,32); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_mu(mask,merge,op1,shift,32); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_mu(mask,merge,op1,shift,32); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_mu(mask,merge,op1,shift,32); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_mu(mask,merge,op1,shift,32); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_mu(mask,merge,op1,shift,32); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_mu(mask,merge,op1,shift,32); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_mu(mask,merge,op1,shift,32); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c > new file mode 100644 > index 00000000000..3d3bf5cae89 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_tu(merge,op1,shift,vl); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_tu(merge,op1,shift,vl); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_tu(merge,op1,shift,vl); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_tu(merge,op1,shift,vl); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_tu(merge,op1,shift,vl); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_tu(merge,op1,shift,vl); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_tu(merge,op1,shift,vl); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_tu(merge,op1,shift,vl); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_tu(merge,op1,shift,vl); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_tu(merge,op1,shift,vl); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_tu(merge,op1,shift,vl); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_tu(merge,op1,shift,vl); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_tu(merge,op1,shift,vl); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_tu(merge,op1,shift,vl); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_tu(merge,op1,shift,vl); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_tu(merge,op1,shift,vl); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_tu(merge,op1,shift,vl); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_tu(merge,op1,shift,vl); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_tu(merge,op1,shift,vl); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_tu(merge,op1,shift,vl); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_tu(merge,op1,shift,vl); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_tu(merge,op1,shift,vl); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c > new file mode 100644 > index 00000000000..1bbc62eec7a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_tu(merge,op1,shift,31); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_tu(merge,op1,shift,31); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_tu(merge,op1,shift,31); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_tu(merge,op1,shift,31); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_tu(merge,op1,shift,31); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_tu(merge,op1,shift,31); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_tu(merge,op1,shift,31); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_tu(merge,op1,shift,31); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_tu(merge,op1,shift,31); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_tu(merge,op1,shift,31); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_tu(merge,op1,shift,31); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_tu(merge,op1,shift,31); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_tu(merge,op1,shift,31); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_tu(merge,op1,shift,31); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_tu(merge,op1,shift,31); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_tu(merge,op1,shift,31); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_tu(merge,op1,shift,31); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_tu(merge,op1,shift,31); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_tu(merge,op1,shift,31); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_tu(merge,op1,shift,31); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_tu(merge,op1,shift,31); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_tu(merge,op1,shift,31); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c > new file mode 100644 > index 00000000000..40d93cd4819 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_tu(merge,op1,shift,32); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_tu(merge,op1,shift,32); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_tu(merge,op1,shift,32); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_tu(merge,op1,shift,32); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_tu(merge,op1,shift,32); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_tu(merge,op1,shift,32); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_tu(merge,op1,shift,32); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_tu(merge,op1,shift,32); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_tu(merge,op1,shift,32); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_tu(merge,op1,shift,32); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_tu(merge,op1,shift,32); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_tu(merge,op1,shift,32); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_tu(merge,op1,shift,32); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_tu(merge,op1,shift,32); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_tu(merge,op1,shift,32); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_tu(merge,op1,shift,32); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_tu(merge,op1,shift,32); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_tu(merge,op1,shift,32); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_tu(merge,op1,shift,32); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_tu(merge,op1,shift,32); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_tu(merge,op1,shift,32); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_tu(merge,op1,shift,32); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c > new file mode 100644 > index 00000000000..13733ab5790 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_tum(mask,merge,op1,shift,vl); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_tum(mask,merge,op1,shift,vl); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c > new file mode 100644 > index 00000000000..de095529474 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_tum(mask,merge,op1,shift,31); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_tum(mask,merge,op1,shift,31); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_tum(mask,merge,op1,shift,31); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_tum(mask,merge,op1,shift,31); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_tum(mask,merge,op1,shift,31); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_tum(mask,merge,op1,shift,31); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_tum(mask,merge,op1,shift,31); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_tum(mask,merge,op1,shift,31); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_tum(mask,merge,op1,shift,31); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_tum(mask,merge,op1,shift,31); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_tum(mask,merge,op1,shift,31); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_tum(mask,merge,op1,shift,31); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_tum(mask,merge,op1,shift,31); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_tum(mask,merge,op1,shift,31); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_tum(mask,merge,op1,shift,31); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_tum(mask,merge,op1,shift,31); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_tum(mask,merge,op1,shift,31); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_tum(mask,merge,op1,shift,31); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_tum(mask,merge,op1,shift,31); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_tum(mask,merge,op1,shift,31); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_tum(mask,merge,op1,shift,31); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_tum(mask,merge,op1,shift,31); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c > new file mode 100644 > index 00000000000..f3ec24517e4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_tum(mask,merge,op1,shift,32); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_tum(mask,merge,op1,shift,32); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_tum(mask,merge,op1,shift,32); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_tum(mask,merge,op1,shift,32); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_tum(mask,merge,op1,shift,32); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_tum(mask,merge,op1,shift,32); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_tum(mask,merge,op1,shift,32); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_tum(mask,merge,op1,shift,32); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_tum(mask,merge,op1,shift,32); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_tum(mask,merge,op1,shift,32); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_tum(mask,merge,op1,shift,32); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_tum(mask,merge,op1,shift,32); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_tum(mask,merge,op1,shift,32); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_tum(mask,merge,op1,shift,32); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_tum(mask,merge,op1,shift,32); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_tum(mask,merge,op1,shift,32); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_tum(mask,merge,op1,shift,32); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_tum(mask,merge,op1,shift,32); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_tum(mask,merge,op1,shift,32); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_tum(mask,merge,op1,shift,32); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_tum(mask,merge,op1,shift,32); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_tum(mask,merge,op1,shift,32); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c > new file mode 100644 > index 00000000000..d17fa8a8cb9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_tumu(mask,merge,op1,shift,vl); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_tumu(mask,merge,op1,shift,vl); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c > new file mode 100644 > index 00000000000..0c3e4e408e5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_tumu(mask,merge,op1,shift,31); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_tumu(mask,merge,op1,shift,31); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c > new file mode 100644 > index 00000000000..8590c65b9f1 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c > @@ -0,0 +1,160 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +vint8mf8_t test___riscv_vsra_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf8_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint8mf4_t test___riscv_vsra_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf4_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint8mf2_t test___riscv_vsra_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8mf2_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint8m1_t test___riscv_vsra_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m1_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint8m2_t test___riscv_vsra_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m2_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint8m4_t test___riscv_vsra_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m4_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint8m8_t test___riscv_vsra_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i8m8_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint16mf4_t test___riscv_vsra_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf4_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint16mf2_t test___riscv_vsra_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16mf2_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint16m1_t test___riscv_vsra_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m1_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint16m2_t test___riscv_vsra_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m2_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint16m4_t test___riscv_vsra_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m4_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint16m8_t test___riscv_vsra_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i16m8_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint32mf2_t test___riscv_vsra_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32mf2_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint32m1_t test___riscv_vsra_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m1_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint32m2_t test___riscv_vsra_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m2_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint32m4_t test___riscv_vsra_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m4_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint32m8_t test___riscv_vsra_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i32m8_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint64m1_t test___riscv_vsra_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m1_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint64m2_t test___riscv_vsra_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m2_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint64m4_t test___riscv_vsra_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m4_tumu(mask,merge,op1,shift,32); > +} > + > + > +vint64m8_t test___riscv_vsra_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) > +{ > + return __riscv_vsra_vx_i64m8_tumu(mask,merge,op1,shift,32); > +} > + > + > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ > -- > 2.36.3 >