From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x930.google.com (mail-ua1-x930.google.com [IPv6:2607:f8b0:4864:20::930]) by sourceware.org (Postfix) with ESMTPS id 0C5B53856DDF for ; Thu, 31 Aug 2023 09:13:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0C5B53856DDF Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x930.google.com with SMTP id a1e0cc1a2514c-79b191089a3so271930241.3 for ; Thu, 31 Aug 2023 02:13:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693473215; x=1694078015; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=lkOM/8soZhKD1lQGQQAiog5CzkfBl89+sKy6+y/GWaU=; b=qxeHdO5Osa8hfdpLkL+wayrELilEN+7HAkI60w1TmDqLK9tiWjEohKh80qRQnv5rjo MwGaDX+FubZpmP0XBfE86S37Ec0VdN/jDlDjpTPheOrh4Q55gjZgsd3G2H2NvgUD3Co4 PXSWxEn+9inrt91HFrhDrLcOIpNrgrIsi2Xss8fAGwHLnDgVV9/J/0YP+oOyD7qK6f4e 928TEOr0DFvjfvdmMDOmeazzt0PL63jrxU3Dv9NEBuMg1QfvOU2XzDgX0Aqgs0iC+rDU RiEhoWjfci8g0OzdtEO3wR6EC0cL1CfF0DnW+cmc/b58zY/oocmeoVqdI77fuajfJmDF raEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693473215; x=1694078015; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lkOM/8soZhKD1lQGQQAiog5CzkfBl89+sKy6+y/GWaU=; b=JAxpBbE5SVR+YC8XfTvNNGg9/6LirB7NXhWX67Xgr26el4l4Oh8ffIl65Bor+XWUjB Cz9WOM4SlxDQ/6rvWgA2Q1TG+rOkZJEIZbFsYgpvBATp3DDuCGNJk7v+FNM0/6CW/vTz PEXMUM5ZkEIxIRQ0Q8ec84uBQHQR0UNHrv8B3taiviq/gtkyx0Y41rHlewyZmHUYbKCV Q6Pw0yopMQTNsKchQ0DyhqfxfekwDB0qa8C2SQUeV0LVike1j6VME9bfR1eUbH+zvm0U 6mxXRzCIP6PnjosCFxgQ+LqjZzMWmW4WlHywLygILc8bHrmlbdD1Bch8Wy4bfYxkynC3 dbxA== X-Gm-Message-State: AOJu0YxbvMGPijTBcp4DZZzCoqx4mdLnQ2YmH1zXK1erziKKeR669Fh0 R49TMoQ3ZPUpd5b8YSmZWCjZ6KN7QeZjM1NiBmkzjnHE X-Google-Smtp-Source: AGHT+IF+ALx59zAid7MfOefQCd9iHZiW/m1ljAzOhdjVqgsWOTIfKFK8rYAvyskWGOKnnjkIaxiguqDf5rcWcCXpSwk= X-Received: by 2002:a67:f998:0:b0:44d:56aa:31b with SMTP id b24-20020a67f998000000b0044d56aa031bmr4225711vsq.28.1693473215170; Thu, 31 Aug 2023 02:13:35 -0700 (PDT) MIME-Version: 1.0 References: <20230831090621.2687116-1-lehua.ding@rivai.ai> In-Reply-To: <20230831090621.2687116-1-lehua.ding@rivai.ai> From: Kito Cheng Date: Thu, 31 Aug 2023 17:13:24 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Change vsetvl tail and mask policy to default policy To: Lehua Ding Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Thu, Aug 31, 2023 at 5:07=E2=80=AFPM Lehua Ding wr= ote: > > This patch change the vsetvl policy to default policy > (returned by get_prefer_mask_policy and get_prefer_tail_policy) instead > fixed policy. Any policy is now returned, allowing change to agnostic > or undisturbed. In the future, users may be able to control the default > policy, such as keeping agnostic by compiler options. > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (IS_AGNOSTIC): Move to here. > * config/riscv/riscv-v.cc (gen_no_side_effects_vsetvl_rtx): > Change to default policy. > * config/riscv/riscv-vector-builtins-bases.cc: Change to default = policy. > * config/riscv/riscv-vsetvl.h (IS_AGNOSTIC): Delete. > * config/riscv/riscv.cc (riscv_print_operand): Use IS_AGNOSTIC to= test. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/binop_vx_constraint-171.c: Adjust. > * gcc.target/riscv/rvv/base/binop_vx_constraint-173.c: Adjust. > * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: New test. > > --- > gcc/config/riscv/riscv-protos.h | 3 +++ > gcc/config/riscv/riscv-v.cc | 4 +++- > gcc/config/riscv/riscv-vector-builtins-bases.cc | 8 ++++---- > gcc/config/riscv/riscv-vsetvl.h | 2 -- > gcc/config/riscv/riscv.cc | 3 +-- > .../riscv/rvv/base/binop_vx_constraint-171.c | 4 ++-- > .../riscv/rvv/base/binop_vx_constraint-173.c | 4 ++-- > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c | 11 +++++++++++ > 8 files changed, 26 insertions(+), 13 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-pro= tos.h > index 92e30a10f3c..e145ee6c69b 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -406,6 +406,9 @@ enum mask_policy > MASK_ANY =3D 2, > }; > > +/* Return true if VALUE is agnostic or any policy. */ > +#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1)) > + > enum class reduction_type > { > UNORDERED, > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 427700192a3..6228ff3d92e 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -1672,9 +1672,11 @@ static rtx > gen_no_side_effects_vsetvl_rtx (machine_mode vmode, rtx vl, rtx avl) > { > unsigned int sew =3D get_sew (vmode); > + rtx tail_policy =3D gen_int_mode (get_prefer_tail_policy (), Pmode); > + rtx mask_policy =3D gen_int_mode (get_prefer_mask_policy (), Pmode); > return gen_vsetvl_no_side_effects (Pmode, vl, avl, gen_int_mode (sew, = Pmode), > gen_int_mode (get_vlmul (vmode), Pmo= de), > - const0_rtx, const0_rtx); > + tail_policy, mask_policy); > } > > /* GET VL * 2 rtx. */ > diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config= /riscv/riscv-vector-builtins-bases.cc > index 54582ee130c..8e679f72392 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc > +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc > @@ -139,11 +139,11 @@ public: > /* LMUL. */ > e.add_input_operand (Pmode, gen_int_mode (get_vlmul (mode), Pmode)); > > - /* TA. */ > - e.add_input_operand (Pmode, gen_int_mode (1, Pmode)); > + /* TAIL_ANY. */ > + e.add_input_operand (Pmode, gen_int_mode (get_prefer_tail_policy (),= Pmode)); > > - /* MU. */ > - e.add_input_operand (Pmode, gen_int_mode (0, Pmode)); > + /* MASK_ANY. */ > + e.add_input_operand (Pmode, gen_int_mode (get_prefer_mask_policy (),= Pmode)); > return e.generate_insn (code_for_vsetvl_no_side_effects (Pmode)); > } > }; > diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vse= tvl.h > index 2a315e45f31..53549abfac5 100644 > --- a/gcc/config/riscv/riscv-vsetvl.h > +++ b/gcc/config/riscv/riscv-vsetvl.h > @@ -21,8 +21,6 @@ along with GCC; see the file COPYING3. If not see > #ifndef GCC_RISCV_VSETVL_H > #define GCC_RISCV_VSETVL_H > > -#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1)) > - > namespace riscv_vector { > > /* Classification of vsetvl instruction. */ > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index d84fa2311fa..8bca8075713 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5246,8 +5246,7 @@ riscv_print_operand (FILE *file, rtx op, int letter= ) > else if (code =3D=3D CONST_INT) > { > /* Tail && Mask policy. */ > - bool agnostic_p =3D UINTVAL (op) & 0x1; > - asm_fprintf (file, "%s", agnostic_p ? "a" : "u"); > + asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "= u"); > } > else > output_operand_lossage ("invalid vector constant"); > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-= 171.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c > index dae5eff42ce..6e8669ae59e 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c > @@ -7,7 +7,7 @@ > /* > ** f1: > ** ... > -** vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au] > +** vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au] > ** ... > ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] > ** ... > @@ -41,7 +41,7 @@ void f1 (void * in, void *out, int64_t x, int n) > /* > ** f2: > ** ... > -** vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au] > +** vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au] > ** ... > ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] > ** ... > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-= 173.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c > index 0d5a2603856..af9c45e942b 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c > @@ -7,7 +7,7 @@ > /* > ** f1: > ** ... > -** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au] > +** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au] > ** ... > ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] > ** ... > @@ -41,7 +41,7 @@ void f1 (void * in, void *out, int64_t x, int vl) > /* > ** f2: > ** ... > -** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au] > +** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au] > ** ... > ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] > ** ... > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/= testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c > new file mode 100644 > index 00000000000..1703c739f5e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d" } */ > + > +#include > + > +size_t foo () > +{ > + return __riscv_vsetvlmax_e8m1 (); > +} > + > +/* { dg-final { scan-assembler-times {\tvsetvli\t[a-x0-9]+,zero,e8,m1,ta= ,ma} 1 } } */ > -- > 2.36.3 >