From: Kito Cheng <kito.cheng@gmail.com>
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] RISC-V: Fix REG_CLASS_CONTENTS.
Date: Mon, 24 Oct 2022 10:18:44 +0800 [thread overview]
Message-ID: <CA+yXCZDERTeQZFDkjqBZZR5h-WFMjajPpr2gzQ8jcJXf8vfU0Q@mail.gmail.com> (raw)
In-Reply-To: <20221024013916.14043-1-juzhe.zhong@rivai.ai>
Committed, thanks for the fix!
On Mon, Oct 24, 2022 at 9:39 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.h (enum reg_class): Fix ALL_REGS.
>
> ---
> gcc/config/riscv/riscv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index acae68ebb2d..37363e975e1 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -516,7 +516,7 @@ enum reg_class
> { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \
> { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe }, /* VNoV0_REGS */ \
> { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* V_REGS */ \
> - { 0xffffffff, 0xffffffff, 0x00000003, 0x00000000 } /* ALL_REGS */ \
> + { 0xffffffff, 0xffffffff, 0x0000000f, 0xffffffff } /* ALL_REGS */ \
> }
>
> /* A C expression whose value is a register class containing hard
> --
> 2.36.1
>
prev parent reply other threads:[~2022-10-24 2:18 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-24 1:39 juzhe.zhong
2022-10-24 2:18 ` Kito Cheng [this message]
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