From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa31.google.com (mail-vk1-xa31.google.com [IPv6:2607:f8b0:4864:20::a31]) by sourceware.org (Postfix) with ESMTPS id 7637E3858C31 for ; Wed, 10 May 2023 08:40:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7637E3858C31 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa31.google.com with SMTP id 71dfb90a1353d-4518d3a9b12so1286830e0c.2 for ; Wed, 10 May 2023 01:40:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683708057; x=1686300057; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=YiQI55qeYkA4nXpCC746gx8bnQdlwEGs7IdS0PNCYe4=; b=atC1YivhS+7rRZekXSQEWdizYwXhajb4s6FqBsWxYGMfFTNoInwM6F7ADFuTkzD+wK JAqlUH8t4XCpw5iv5XJzYTGIPyOXaXcMtbJ/ijVj6QQzU5raZ+ZUrrovq/EdvWsN8QRN sdkvrKYu0jhIrMUGrPY5ri2Y5FZgA3X578vAYiG6iKo6WYsUWHt/dX937d/MBxrx9K6Y tbPFYytJpCddJHXZJx6Rg63Na9O4nsDhzGsgUZWQHHojod0hyQhF5i8tqD1mo6kXPbsg Tgp2TsZI3wanZZj5Y5WJU2URGv8wfgSQiToatTIPUCS2SMEMsq+3xH+c9H0nqBUYVtLo trhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683708057; x=1686300057; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YiQI55qeYkA4nXpCC746gx8bnQdlwEGs7IdS0PNCYe4=; b=CrlzXqK1CxlnG2k9aknXyWIWkWA1+hnSu6fU0oHeBjgMXH1aQkWd512gnrLvmjcGGc y9FrYoCwy7Xamw0f1Z7L86ZjrxMLLAZT193BkOxeseu077XPZ67SOuZs4/vJIF+TsWR+ MFUwwyYscCynNjDZrGF3AUCSFP7JUIl1hhx7OZkTkKPLLY+3XmD+U8tYULPFrlchc6Zq 0E/NocfohadLUy1Dj1kj2I8ssEK32gQhQgUIwtJAjtCfMlja+m7paRuNlIpBSc1WRDpF vDz5DqBRabC5oyxwl3yMYt/yhB3nZaWSVnwf26BiIR2EqU7kYp1fg6bQQcXg3yBk5aJi itDg== X-Gm-Message-State: AC+VfDx/EqRopK+wQOgg86gpfjGW8w7zpz3/EIx2fJXp+PgmOAQnLGCP hFJu9eU5fEgkMCroHwunYMPRCtUvBjRu3d8PHMp3HFrN X-Google-Smtp-Source: ACHHUZ5VT/GkJ0J0o1Jb6aq3NxUdBaIDLJp+nlNEfxtcuTa2AWykVqO6Kgnn7I2o6CI8Ocw9INEWRxaMfDfhsxbFyf8= X-Received: by 2002:a1f:e243:0:b0:44f:8aba:7104 with SMTP id z64-20020a1fe243000000b0044f8aba7104mr3987497vkg.0.1683708056409; Wed, 10 May 2023 01:40:56 -0700 (PDT) MIME-Version: 1.0 References: <20230510040213.7313-1-xuli1@eswincomputing.com> In-Reply-To: From: Kito Cheng Date: Wed, 10 May 2023 16:40:44 +0800 Message-ID: Subject: Re: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0. To: "juzhe.zhong@rivai.ai" Cc: Li Xu , gcc-patches , palmer Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed, thanks for catching this issue :) On Wed, May 10, 2023 at 12:08=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > LGTM. Let's wait for kito's feedback. > Thanks :) > > > > juzhe.zhong@rivai.ai > > From: Li Xu > Date: 2023-05-10 12:02 > To: gcc-patches > CC: kito.cheng; palmer; juzhe.zhong; Li Xu > Subject: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s = instructions satisfying REG_P(operand[1]) in -O0. > This issue happens is because the operand1 of scalar move can be > REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to > not insert the vsetvl instruction correctly, and the compiler crashes. > > Consider this following case: > int16_t foo1 (void *base, size_t vl) > { > int16_t maxVal =3D __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (= base, vl)); > return maxVal; > } > > Before this patch: > bug.c:15:1: internal compiler error: Segmentation fault > 15 | } > | ^ > 0x145d723 crash_signal > ../.././riscv-gcc/gcc/toplev.cc:314 > 0x22929dd const_csr_operand(rtx_def*, machine_mode) > ../.././riscv-gcc/gcc/config/riscv/predicates.md:44 > 0x2292a21 csr_operand(rtx_def*, machine_mode) > ../.././riscv-gcc/gcc/config/riscv/predicates.md:46 > 0x23dfbb0 recog_356 > ../.././riscv-gcc/gcc/config/riscv/iterators.md:72 > 0x23efecd recog(rtx_def*, rtx_insn*, int*) > ../.././riscv-gcc/gcc/config/riscv/iterators.md:89 > 0xdddc15 recog_memoized(rtx_insn*) > ../.././riscv-gcc/gcc/recog.h:273 > > After this patch: > vsetivli zero,0,e16,m1,ta,ma > vmv.x.s a5,v1 > > gcc/ChangeLog: > > * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv= .x.s intruction replace null avl with (const_int 0). > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/scalar_move-10.c: New test. > * gcc.target/riscv/rvv/base/scalar_move-11.c: New test. > --- > gcc/config/riscv/riscv-vsetvl.cc | 5 +++ > .../riscv/rvv/base/scalar_move-10.c | 31 +++++++++++++++++++ > .../riscv/rvv/base/scalar_move-11.c | 20 ++++++++++++ > 3 files changed, 56 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11= .c > > diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vs= etvl.cc > index d4d6f336ef9..14ebae1f3f6 100644 > --- a/gcc/config/riscv/riscv-vsetvl.cc > +++ b/gcc/config/riscv/riscv-vsetvl.cc > @@ -618,6 +618,11 @@ static rtx > gen_vsetvl_pat (enum vsetvl_type insn_type, const vl_vtype_info &info, rt= x vl) > { > rtx avl =3D info.get_avl (); > + /* if optimization =3D=3D 0 and the instruction is vmv.x.s/vfmv.f.s, > + set the value of avl to (const_int 0) so that VSETVL PASS will > + insert vsetvl correctly.*/ > + if (info.has_avl_no_reg ()) > + avl =3D GEN_INT (0); > rtx sew =3D gen_int_mode (info.get_sew (), Pmode); > rtx vlmul =3D gen_int_mode (info.get_vlmul (), Pmode); > rtx ta =3D gen_int_mode (info.get_ta (), Pmode); > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c b/g= cc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c > new file mode 100644 > index 00000000000..9760d77fb22 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c > @@ -0,0 +1,31 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O0" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "riscv_vector.h" > + > +/* > +** foo1: > +** ... > +** vsetivli\tzero,0,e16,m1,t[au],m[au] > +** vmv.x.s\t[a-x0-9]+,v[0-9]+ > +** ... > +*/ > +int16_t foo1 (void *base, size_t vl) > +{ > + int16_t maxVal =3D __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 = (base, vl)); > + return maxVal; > +} > + > +/* > +** foo2: > +** ... > +** vsetivli\tzero,0,e32,m1,t[au],m[au] > +** vfmv.f.s\tf[a-x0-9]+,v[0-9]+ > +** ... > +*/ > +float foo2 (void *base, size_t vl) > +{ > + float maxVal =3D __riscv_vfmv_f_s_f32m1_f32 (__riscv_vle32_v_f32m1 (= base, vl)); > + return maxVal; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c b/g= cc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c > new file mode 100644 > index 00000000000..8036acd0a52 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32d -O0" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "riscv_vector.h" > + > +/* > +** foo: > +** ... > +** vsetivli\tzero,0,e64,m4,t[au],m[au] > +** vmv.x.s\t[a-x0-9]+,v[0-9]+ > +** vsetivli\tzero,0,e64,m4,t[au],m[au] > +** vmv.x.s\t[a-x0-9]+,v[0-9]+ > +** ... > +*/ > +int16_t foo (void *base, size_t vl) > +{ > + int16_t maxVal =3D __riscv_vmv_x_s_i64m4_i64 (__riscv_vle64_v_i64m4 = (base, vl)); > + return maxVal; > +} > -- > 2.17.1 > >