Re: [PATCH v2] Docs: Add vector register constarint for asm operands

[Kito Cheng <kito.cheng@gmail.com>]

committed

On Thu, Apr 27, 2023 at 10:02 PM Kito Cheng via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> `vr`, `vm` and `vd` constarint for vector register constarint, those 3
> constarint has implemented on LLVM as well.
>
> gcc/ChangeLog:
>
>         * doc/md.texi (RISC-V): Add vr, vm, vd constarint.
>
> ---
>
> V2 changes:
> - Drop unrelated changes.
>
> ---
>  gcc/doc/md.texi | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index 07bf8bdebffb..cc4a93a87638 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -3535,6 +3535,15 @@ An address that is held in a general-purpose register.
>  @item S
>  A constraint that matches an absolute symbolic address.
>
> +@item vr
> +A vector register (if available)..
> +
> +@item vd
> +A vector register, excluding v0 (if available).
> +
> +@item vm
> +A vector register, only v0 (if available).
> +
>  @end table
>
>  @item RX---@file{config/rx/constraints.md}
> --
> 2.39.2
>