From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa2e.google.com (mail-vk1-xa2e.google.com [IPv6:2607:f8b0:4864:20::a2e]) by sourceware.org (Postfix) with ESMTPS id 9E3343858D37 for ; Fri, 28 Apr 2023 07:17:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9E3343858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa2e.google.com with SMTP id 71dfb90a1353d-440638ad528so3258769e0c.3 for ; Fri, 28 Apr 2023 00:17:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682666255; x=1685258255; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=psz/o/xs50akFPUijeMRSGtxhlUHDaTs3NNTqPxcqP4=; b=gx6JY7dYzH5124jIg4VOMYbqFDtxfWzYCsC4DEbwnFPgPiWwzrf92ZjuV5p4dwNhOS PT2JIzqXuRRY7BoC+OgtBqEQpOQ/AyvG0RzLyyGRYclTBQqN9TT96dzinNqonKSFdG3z Yi3XAzUxND92U9C7aH+/GTykOu0Liqzi6HfU13KXDdCgEMH5xEDyuohgaYIzS7Z9P8hz ZifjXhaESCHDdW5JR2UBb8Nk/r1EEQoGsgDD7MQKSRua9smzNx8C9UgdBboFG6vIkQ59 wJY/mEVHyTKoV5W5kcmYTrF2xX0LoFh7CEPbYgl7bAntE/HW8jkZtfPg+JaX9h6dmysY L24A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682666255; x=1685258255; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=psz/o/xs50akFPUijeMRSGtxhlUHDaTs3NNTqPxcqP4=; b=Yo+wRDaxCVZr8JBeFDMrdQkqkihV9YereuAVuHxmi8ci/ZgbP65EqnIly2PgMjuBok n4+tJEaeSnF9Cw1VrobUkx0LqDhD51bMBoOv9VJILeBZ1X7HUg/KTDxCuV0mhfKpFZ3I 0DBkIEx7rZFbO/bb4XbSBOX8Tz6yqw1VTi33m5NHJ4YkVgT1wYIZ2V8025uTvEk5/mXn GPS1eC3CzvhjNrCNW43ZK0MZjNEtpKaP6dPGLe2btuErIeRIUorlbCcmIIznvQ/dcaJ4 v05z1N2Q/jKPkU3BS5SVGqC8PW74YeVDK4ZkUe0oLxsO6YyXv9S/OVpE+6lengmOn8ZQ lDJg== X-Gm-Message-State: AC+VfDyybT388hdB8bEDcqJPRPuRFKQrm36OH3M8onNeyuJlLAcrUrCp 0a0gV4V9muwArJV5ZX4Y42bm6HkPLxqOQ+UnPD4= X-Google-Smtp-Source: ACHHUZ4IPbSyvV9pyOxOi/j1TUe/XRd0yzw6zeT4FcJGbUTi4hlx580f/4/vXyODqs6c7w3KYV9SgU4ZBfrDWEd0URw= X-Received: by 2002:a1f:bf92:0:b0:43b:eed8:98a4 with SMTP id p140-20020a1fbf92000000b0043beed898a4mr1859898vkf.7.1682666254638; Fri, 28 Apr 2023 00:17:34 -0700 (PDT) MIME-Version: 1.0 References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> <20230428061210.2988035-2-christoph.muellner@vrull.eu> In-Reply-To: <20230428061210.2988035-2-christoph.muellner@vrull.eu> From: Kito Cheng Date: Fri, 28 Apr 2023 15:17:23 +0800 Message-ID: Subject: Re: [PATCH 01/11] riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extu To: Christoph Muellner Cc: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: ok On Fri, Apr 28, 2023 at 2:13=E2=80=AFPM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > The current support of the bitfield-extraction instructions > th.ext and th.extu (XTheadBb extension) only covers sign_extract > and zero_extract. This patch add support for sign_extend and > zero_extend to avoid any shifts for sign or zero extensions. > > gcc/ChangeLog: > > * config/riscv/riscv.md: No base-ISA extension splitter for XThea= d*. > * config/riscv/thead.md (*extend2_th_ex= t): > New XThead extension INSN. > (*zero_extendsidi2_th_extu): New XThead extension INSN. > (*zero_extendhi2_th_extu): New XThead extension INSN. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/xtheadbb-ext-1.c: New test. > * gcc.target/riscv/xtheadbb-extu-1.c: New test. > > Signed-off-by: Christoph M=C3=BCllner > --- > gcc/config/riscv/riscv.md | 6 +- > gcc/config/riscv/thead.md | 31 +++++++++ > .../gcc.target/riscv/xtheadbb-ext-1.c | 67 +++++++++++++++++++ > .../gcc.target/riscv/xtheadbb-extu-1.c | 67 +++++++++++++++++++ > 4 files changed, 168 insertions(+), 3 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 1fb29da8a0b..f4cc99187ed 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -1368,7 +1368,7 @@ (define_insn_and_split "*zero_extendsidi2_internal" > [(set (match_operand:DI 0 "register_operand" "=3Dr,r") > (zero_extend:DI > (match_operand:SI 1 "nonimmediate_operand" " r,m")))] > - "TARGET_64BIT && !TARGET_ZBA > + "TARGET_64BIT && !TARGET_ZBA && !TARGET_XTHEADBB > && !(register_operand (operands[1], SImode) > && reg_or_subregno (operands[1]) =3D=3D VL_REGNUM)" > "@ > @@ -1395,7 +1395,7 @@ (define_insn_and_split "*zero_extendhi2" > [(set (match_operand:GPR 0 "register_operand" "=3Dr,r") > (zero_extend:GPR > (match_operand:HI 1 "nonimmediate_operand" " r,m")))] > - "!TARGET_ZBB" > + "!TARGET_ZBB && !TARGET_XTHEADBB" > "@ > # > lhu\t%0,%1" > @@ -1451,7 +1451,7 @@ (define_insn_and_split "*extend2" > [(set (match_operand:SUPERQI 0 "register_operand" "=3Dr,r") > (sign_extend:SUPERQI > (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))] > - "!TARGET_ZBB" > + "!TARGET_ZBB && !TARGET_XTHEADBB" > "@ > # > l\t%0,%1" > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md > index 0623607d3dc..6a06d0dfcf2 100644 > --- a/gcc/config/riscv/thead.md > +++ b/gcc/config/riscv/thead.md > @@ -59,6 +59,17 @@ (define_insn "*th_ext4" > [(set_attr "type" "bitmanip") > (set_attr "mode" "")]) > > +(define_insn "*extend2_th_ext" > + [(set (match_operand:SUPERQI 0 "register_operand" "=3Dr,r") > + (sign_extend:SUPERQI > + (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))] > + "TARGET_XTHEADBB" > + "@ > + th.ext\t%0,%1,15,0 > + l\t%0,%1" > + [(set_attr "type" "bitmanip,load") > + (set_attr "mode" "")]) > + > (define_insn "*th_extu4" > [(set (match_operand:GPR 0 "register_operand" "=3Dr") > (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r") > @@ -72,6 +83,26 @@ (define_insn "*th_extu4" > [(set_attr "type" "bitmanip") > (set_attr "mode" "")]) > > +(define_insn "*zero_extendsidi2_th_extu" > + [(set (match_operand:DI 0 "register_operand" "=3Dr,r") > + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")= ))] > + "TARGET_64BIT && TARGET_XTHEADBB" > + "@ > + th.extu\t%0,%1,31,0 > + lwu\t%0,%1" > + [(set_attr "type" "bitmanip,load") > + (set_attr "mode" "SI")]) > + > +(define_insn "*zero_extendhi2_th_extu" > + [(set (match_operand:GPR 0 "register_operand" "=3Dr,r") > + (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m"= )))] > + "TARGET_XTHEADBB" > + "@ > + th.extu\t%0,%1,15,0 > + lhu\t%0,%1" > + [(set_attr "type" "bitmanip,load") > + (set_attr "mode" "HI")]) > + > (define_insn "*th_clz2" > [(set (match_operand:X 0 "register_operand" "=3Dr") > (clz:X (match_operand:X 1 "register_operand" "r")))] > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c b/gcc/testsu= ite/gcc.target/riscv/xtheadbb-ext-1.c > new file mode 100644 > index 00000000000..02f6ec1417d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c > @@ -0,0 +1,67 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gc_xtheadbb" { target { rv64 } } } */ > +/* { dg-options "-march=3Drv32gc_xtheadbb" { target { rv32 } } } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ > + > +long sext64_32(int s32) > +{ > + return s32; > +} > + > +long sext64_16(short s16) > +{ > + return s16; > +} > + > +long sext64_8(char s8) > +{ > + return s8; > +} > + > +int sext32_64(long s64) > +{ > + return s64; > +} > + > +int sext32_16(short s16) > +{ > + return s16; > +} > + > +int sext32_8(char s8) > +{ > + return s8; > +} > + > +short sext16_64(long s64) > +{ > + return s64; > +} > + > +short sext16_32(int s32) > +{ > + return s32; > +} > + > +short sext16_8(char s8) > +{ > + return s8; > +} > + > +char sext8_64(long s64) > +{ > + return s64; > +} > + > +char sext8_32(int s32) > +{ > + return s32; > +} > + > +char sext8_16(short s16) > +{ > + return s16; > +} > + > +/* { dg-final { scan-assembler-not "slli" } } */ > +/* { dg-final { scan-assembler-not "srli" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c b/gcc/tests= uite/gcc.target/riscv/xtheadbb-extu-1.c > new file mode 100644 > index 00000000000..01e3eda7df2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c > @@ -0,0 +1,67 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gc_xtheadbb" { target { rv32 } } } */ > +/* { dg-options "-march=3Drv64gc_xtheadbb" { target { rv64 } } } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ > + > +unsigned long zext64_32(unsigned int u32) > +{ > + return u32; //th.extu a0, a0, 31, 0 > +} > + > +unsigned long zext64_16(unsigned short u16) > +{ > + return u16; > +} > + > +unsigned long zext64_8(unsigned char u8) > +{ > + return u8; > +} > + > +unsigned int zext32_64(unsigned long u64) > +{ > + return u64; > +} > + > +unsigned int zext32_16(unsigned short u16) > +{ > + return u16; > +} > + > +unsigned int zext32_8(unsigned char u8) > +{ > + return u8; > +} > + > +unsigned short zext16_64(unsigned long u64) > +{ > + return u64; > +} > + > +unsigned short zext16_32(unsigned int u32) > +{ > + return u32; > +} > + > +unsigned short zext16_8(unsigned char u8) > +{ > + return u8; > +} > + > +unsigned char zext8_64(unsigned long u64) > +{ > + return u64; > +} > + > +unsigned char zext8_32(unsigned int u32) > +{ > + return u32; > +} > + > +unsigned char zext8_16(unsigned short u16) > +{ > + return u16; > +} > + > +/* { dg-final { scan-assembler-not "slli" } } */ > +/* { dg-final { scan-assembler-not "srli" } } */ > -- > 2.40.1 >