From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x934.google.com (mail-ua1-x934.google.com [IPv6:2607:f8b0:4864:20::934]) by sourceware.org (Postfix) with ESMTPS id 1B40E3858D37 for ; Wed, 24 May 2023 03:20:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1B40E3858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x934.google.com with SMTP id a1e0cc1a2514c-783f17f0a00so193719241.2 for ; Tue, 23 May 2023 20:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684898434; x=1687490434; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=rubnCYe0xXEeosfVrI9amly3oQeWgqcOOUyaXTSiakM=; b=PyX+ISF3o20vPsAT0o5DvpouoWidXFOTFFE7Q0NckJwf8xRKtdfnd2krdPG+UzKBfy +ISvpXKft9yJ9o3IANMi9AJ7ZCrhNFYMfewtiuj/PXt6RMbSPH9mzsXNWI5j/Lw4PCoh /KExQydu/Ts+ivoXQea9aGiv/2bk4Z1Y9aNS7MgRLN9mrVNGa/EESgz2o1CwebbXXiWq Q5QEOIBhVjd8hirnCA0tXluzmXJ+79I1a/B7FtalcsQ27SpPyAKiZ0MO/CeKZFdF2Gpk FJrN/Ymsc/pdCQgB35nWk05XX9c5heAOUd81ZRyIpLSVZPdvmQM4WwCbcO+hMAi9jtkE O/yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684898434; x=1687490434; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=rubnCYe0xXEeosfVrI9amly3oQeWgqcOOUyaXTSiakM=; b=lqx8YmTNxdgLXAI0HcApOQR7a9Oz8ZqJioAQtKhvYhakqCU1ZvR2SO9hNa7XlCfAFI tQtzHp5O7XlEwH9IrdSKtJeFhmtotvaLEC8+/R7wdLnrVnjKOUM7Cz6g24OwqbAS1RE/ sj9mdx6ldPf7UsRNHbvj1IcWgOvTdYGt8S+Jkcwqw5PmPV8/dYmn+U+9yslg0GaeriDg bFsULdE/BPjZu96Xk2LMaqNnHDVmSXIQrCAU2qWJxaVyZzGw2OY6VV4dl9YiUvs5PcZi svHG0psNpbZ30dXsVSBh6lpO04c+tEOu3cbuagow6LEJ2wR9EpG67JzrFxyrVtK4QwCk FoBQ== X-Gm-Message-State: AC+VfDzTpd4z6e5ag4f7WAmd6VXD6TZLxoq9ZwoctvOLKBF7DbSAi94J io+PNYw7i5bRtYnKB/sR9R3tRKHv2/3PleoR2L4= X-Google-Smtp-Source: ACHHUZ6//4AqsBUlPahiVqZPyrMPDWt1C2E/Sy1MLaSR2Lr3CiIQ2kVrm+BhEiqVCeiYsIZzW1OfN3g9XxzB3smMIDY= X-Received: by 2002:a67:e25a:0:b0:435:84bc:805a with SMTP id w26-20020a67e25a000000b0043584bc805amr4644389vse.25.1684898433863; Tue, 23 May 2023 20:20:33 -0700 (PDT) MIME-Version: 1.0 References: <20230523135007.682279-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230523135007.682279-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Wed, 24 May 2023 11:20:22 +0800 Message-ID: Subject: Re: [PATCH V2] RISC-V: Add RVV comparison autovectorization To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Richard Sandiford Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > +void > +expand_vec_cmp (rtx target, rtx_code code, rtx mask, rtx maskoff, rtx op0, > + rtx op1) > ... > + rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1); > + rtx ops[RVV_CMP_OP + 2] = {target, mask, maskoff, cmp, op0, op1}; > + emit_vlmax_cmp_insn (icode, RVV_CMP_OP + 2, ops); It's too magic. > +/* This function emits cmp instruction. */ > +void > +emit_vlmax_cmp_insn (unsigned icode, int op_num, rtx *ops) > +{ > + machine_mode mode = GET_MODE (ops[0]); > + bool fully_unmasked_p = op_num == RVV_CMP_OP ? true : false; > + bool use_real_merge_p = op_num == RVV_CMP_OP ? false : true; Don't do that, plz separate break this function into two. > + /* We have a maximum of 11 operands for RVV instruction patterns according to > + * vector.md. */ > + insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, > + /*FULLY_UNMASKED_P*/ fully_unmasked_p, > + /*USE_REAL_MERGE_P*/ use_real_merge_p, > + /*HAS_AVL_P*/ true, > + /*VLMAX_P*/ true, > + /*DEST_MODE*/ mode, /*MASK_MODE*/ mode); > + e.set_policy (op_num == RVV_CMP_OP ? MASK_UNDISTURBED : MASK_ANY); > + e.emit_insn ((enum insn_code) icode, ops); > +} > + > /* Expand series const vector. */ > > void > +void > +expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1) > +{ > + machine_mode mask_mode = GET_MODE (target); > + machine_mode data_mode = GET_MODE (op0); > + insn_code icode = get_cmp_insn_code (code, data_mode); > + > + if (code == LTGT) > + { > + rtx gt = gen_reg_rtx (mask_mode); > + rtx lt = gen_reg_rtx (mask_mode); > + expand_vec_cmp (gt, GT, op0, op1); > + expand_vec_cmp (lt, LT, op0, op1); > + icode = code_for_pred (IOR, mask_mode); > + rtx ops[3] = {target, gt, lt}; rtx ops[] = {target, gt, lt}; > + emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops); > + return; > + } > + > + rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1); > + rtx ops[RVV_CMP_OP] = {target, cmp, op0, op1}; rtx ops[] = {target, cmp, op0, op1}; > + emit_vlmax_cmp_insn (icode, RVV_CMP_OP, ops); > +} > + > + /* There is native support for the inverse comparison. */ > + code = reverse_condition_maybe_unordered (code); > + if (code == ORDERED) > + emit_move_insn (target, eq0); > + else > + expand_vec_cmp (eq0, code, eq0, eq0, op0, op1); > + > + if (can_invert_p) > + { > + emit_move_insn (target, eq0); > + return true; > + } > + insn_code icode = code_for_pred_not (mask_mode); > + rtx ops[RVV_UNOP] = {target, eq0}; > + emit_vlmax_insn (icode, RVV_UNOP, ops); rtx ops[] = {target, eq0};