From: Kito Cheng <kito.cheng@gmail.com>
To: "Maciej W. Rozycki" <macro@embecosm.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
Andrew Waterman <andrew@sifive.com>
Subject: Re: [PATCH] RISC-V/testsuite: Run target testing over all the usual optimization levels
Date: Tue, 8 Feb 2022 00:22:37 +0800 [thread overview]
Message-ID: <CA+yXCZDMcgL1ggmOk7XWT_FUZaOix0=BaHnSxceuoL3UW0V=YA@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.20.2201312153300.11348@tpp.orcam.me.uk>
Hi Maciej:
Thanks for doing this, OK to trunk.
On Tue, Feb 1, 2022 at 7:04 AM Maciej W. Rozycki <macro@embecosm.com> wrote:
>
> Use `gcc-dg-runtest' test driver rather than `dg-runtest' to run the
> RISC-V testsuite as several targets already do. Adjust test options
> across individual test cases accordingly where required.
>
> As some tests want to be run at `-Og', add a suitable optimization
> variant via ADDITIONAL_TORTURE_OPTIONS, and include the moderately
> recent `-Oz' variant as well.
>
> * testsuite/gcc.target/riscv/riscv.exp: Use `gcc-dg-runtest'
> rather than `dg-runtest'. Add `-Og -g' and `-Oz' variants via
> ADDITIONAL_TORTURE_OPTIONS.
> * testsuite/gcc.target/riscv/arch-1.c: Adjust test options
> accordingly.
> * testsuite/gcc.target/riscv/arch-10.c: Likewise.
> * testsuite/gcc.target/riscv/arch-11.c: Likewise.
> * testsuite/gcc.target/riscv/arch-12.c: Likewise.
> * testsuite/gcc.target/riscv/arch-2.c: Likewise.
> * testsuite/gcc.target/riscv/arch-3.c: Likewise.
> * testsuite/gcc.target/riscv/arch-4.c: Likewise.
> * testsuite/gcc.target/riscv/arch-5.c: Likewise.
> * testsuite/gcc.target/riscv/arch-6.c: Likewise.
> * testsuite/gcc.target/riscv/arch-7.c: Likewise.
> * testsuite/gcc.target/riscv/arch-8.c: Likewise.
> * testsuite/gcc.target/riscv/arch-9.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-1.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-10.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-11.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-12.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-13.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-14.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-15.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-16.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-17.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-2.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-3.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-4.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-5.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-7.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-8.c: Likewise.
> * testsuite/gcc.target/riscv/attribute-9.c: Likewise.
> * testsuite/gcc.target/riscv/interrupt-1.c: Likewise.
> * testsuite/gcc.target/riscv/interrupt-2.c: Likewise.
> * testsuite/gcc.target/riscv/interrupt-3.c: Likewise.
> * testsuite/gcc.target/riscv/interrupt-4.c: Likewise.
> * testsuite/gcc.target/riscv/interrupt-conflict-mode.c: Likewise.
> * testsuite/gcc.target/riscv/interrupt-debug.c: Likewise.
> * testsuite/gcc.target/riscv/interrupt-mmode.c: Likewise.
> * testsuite/gcc.target/riscv/interrupt-smode.c: Likewise.
> * testsuite/gcc.target/riscv/interrupt-umode.c: Likewise.
> * testsuite/gcc.target/riscv/li.c: Likewise.
> * testsuite/gcc.target/riscv/load-immediate.c: Likewise.
> * testsuite/gcc.target/riscv/losum-overflow.c: Likewise.
> * testsuite/gcc.target/riscv/mcpu-6.c: Likewise.
> * testsuite/gcc.target/riscv/mcpu-7.c: Likewise.
> * testsuite/gcc.target/riscv/pr102957.c: Likewise.
> * testsuite/gcc.target/riscv/pr103302.c: Likewise.
> * testsuite/gcc.target/riscv/pr104140.c: Likewise.
> * testsuite/gcc.target/riscv/pr84660.c: Likewise.
> * testsuite/gcc.target/riscv/pr93202.c: Likewise.
> * testsuite/gcc.target/riscv/pr93304.c: Likewise.
> * testsuite/gcc.target/riscv/pr95252.c: Likewise.
> * testsuite/gcc.target/riscv/pr95683.c: Likewise.
> * testsuite/gcc.target/riscv/pr98777.c: Likewise.
> * testsuite/gcc.target/riscv/pr99702.c: Likewise.
> * testsuite/gcc.target/riscv/predef-1.c: Likewise.
> * testsuite/gcc.target/riscv/predef-10.c: Likewise.
> * testsuite/gcc.target/riscv/predef-11.c: Likewise.
> * testsuite/gcc.target/riscv/predef-12.c: Likewise.
> * testsuite/gcc.target/riscv/predef-13.c: Likewise.
> * testsuite/gcc.target/riscv/predef-14.c: Likewise.
> * testsuite/gcc.target/riscv/predef-15.c: Likewise.
> * testsuite/gcc.target/riscv/predef-16.c: Likewise.
> * testsuite/gcc.target/riscv/predef-2.c: Likewise.
> * testsuite/gcc.target/riscv/predef-3.c: Likewise.
> * testsuite/gcc.target/riscv/predef-4.c: Likewise.
> * testsuite/gcc.target/riscv/predef-5.c: Likewise.
> * testsuite/gcc.target/riscv/predef-6.c: Likewise.
> * testsuite/gcc.target/riscv/predef-7.c: Likewise.
> * testsuite/gcc.target/riscv/predef-8.c: Likewise.
> * testsuite/gcc.target/riscv/promote-type-for-libcall.c: Likewise.
> * testsuite/gcc.target/riscv/save-restore-1.c: Likewise.
> * testsuite/gcc.target/riscv/save-restore-2.c: Likewise.
> * testsuite/gcc.target/riscv/save-restore-3.c: Likewise.
> * testsuite/gcc.target/riscv/save-restore-4.c: Likewise.
> * testsuite/gcc.target/riscv/save-restore-6.c: Likewise.
> * testsuite/gcc.target/riscv/save-restore-7.c: Likewise.
> * testsuite/gcc.target/riscv/save-restore-8.c: Likewise.
> * testsuite/gcc.target/riscv/save-restore-9.c: Likewise.
> * testsuite/gcc.target/riscv/shift-and-1.c: Likewise.
> * testsuite/gcc.target/riscv/shift-and-2.c: Likewise.
> * testsuite/gcc.target/riscv/shift-shift-1.c: Likewise.
> * testsuite/gcc.target/riscv/shift-shift-2.c: Likewise.
> * testsuite/gcc.target/riscv/shift-shift-3.c: Likewise.
> * testsuite/gcc.target/riscv/shift-shift-4.c: Likewise.
> * testsuite/gcc.target/riscv/shift-shift-5.c: Likewise.
> * testsuite/gcc.target/riscv/shorten-memrefs-1.c: Likewise.
> * testsuite/gcc.target/riscv/shorten-memrefs-2.c: Likewise.
> * testsuite/gcc.target/riscv/shorten-memrefs-3.c: Likewise.
> * testsuite/gcc.target/riscv/shorten-memrefs-4.c: Likewise.
> * testsuite/gcc.target/riscv/shorten-memrefs-5.c: Likewise.
> * testsuite/gcc.target/riscv/shorten-memrefs-6.c: Likewise.
> * testsuite/gcc.target/riscv/shorten-memrefs-7.c: Likewise.
> * testsuite/gcc.target/riscv/shorten-memrefs-8.c: Likewise.
> * testsuite/gcc.target/riscv/switch-qi.c: Likewise.
> * testsuite/gcc.target/riscv/switch-si.c: Likewise.
> * testsuite/gcc.target/riscv/weak-1.c: Likewise.
> * testsuite/gcc.target/riscv/zba-adduw.c: Likewise.
> * testsuite/gcc.target/riscv/zba-shNadd-01.c: Likewise.
> * testsuite/gcc.target/riscv/zba-shNadd-02.c: Likewise.
> * testsuite/gcc.target/riscv/zba-shNadd-03.c: Likewise.
> * testsuite/gcc.target/riscv/zba-slliuw.c: Likewise.
> * testsuite/gcc.target/riscv/zba-zextw.c: Likewise.
> * testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c: Likewise.
> * testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c: Likewise.
> * testsuite/gcc.target/riscv/zbb-li-rotr.c: Likewise.
> * testsuite/gcc.target/riscv/zbb-min-max.c: Likewise.
> * testsuite/gcc.target/riscv/zbb-rol-ror-01.c: Likewise.
> * testsuite/gcc.target/riscv/zbb-rol-ror-02.c: Likewise.
> * testsuite/gcc.target/riscv/zbb-rol-ror-03.c: Likewise.
> * testsuite/gcc.target/riscv/zbbw.c: Likewise.
> * testsuite/gcc.target/riscv/zbs-bclr.c: Likewise.
> * testsuite/gcc.target/riscv/zbs-bext.c: Likewise.
> * testsuite/gcc.target/riscv/zbs-binv.c: Likewise.
> * testsuite/gcc.target/riscv/zbs-bset.c: Likewise.
> * testsuite/gcc.target/riscv/zero-extend-1.c: Likewise.
> * testsuite/gcc.target/riscv/zero-extend-2.c: Likewise.
> * testsuite/gcc.target/riscv/zero-extend-3.c: Likewise.
> * testsuite/gcc.target/riscv/zero-extend-4.c: Likewise.
> * testsuite/gcc.target/riscv/zero-extend-5.c: Likewise.
> ---
> Hi,
>
> No regressions in `riescv64-linux-gnu' testing.
>
> I have marked variants for exclusion that legitimately fail (e.g. the
> optimisation required is not enabled for the level in question, or debug
> information interferes with expected output produced) or do not fail but
> make no sense (e.g. entirely different code produced at `-O0', so there's
> no point to run `scan-assembler-not' over it).
>
> I think if we are to switch to `gcc-dg-runtest', then it's best to do
> that while the number of the test cases we have is still relatively small,
> as this is invevitably going to grow with time.
>
> As to adding `-Og -g' and `-Oz', this should probably be done globally in
> gcc-dg.exp, but such a change would affect all the interested targets at
> once and would require a huge one-by-one test case review. Therefore I
> think adding targets one by one instead is more feasible, and then we can
> switch once all the targets have. I'll look into the VAX target myself.
>
> Questions, concerns, thoughts? Otherwise OK to apply even at stage 4, as
> not a code change?
>
> Maciej
> ---
> gcc/testsuite/gcc.target/riscv/arch-1.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-10.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-11.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-12.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-2.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-3.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-4.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-5.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-6.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-7.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-8.c | 2 +-
> gcc/testsuite/gcc.target/riscv/arch-9.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-1.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-10.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-11.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-12.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-13.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-14.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-2.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-3.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-4.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-5.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-7.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-8.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-9.c | 2 +-
> gcc/testsuite/gcc.target/riscv/interrupt-1.c | 2 +-
> gcc/testsuite/gcc.target/riscv/interrupt-2.c | 2 +-
> gcc/testsuite/gcc.target/riscv/interrupt-3.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/interrupt-4.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c | 2 +-
> gcc/testsuite/gcc.target/riscv/interrupt-debug.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/interrupt-mmode.c | 2 +-
> gcc/testsuite/gcc.target/riscv/interrupt-smode.c | 2 +-
> gcc/testsuite/gcc.target/riscv/interrupt-umode.c | 2 +-
> gcc/testsuite/gcc.target/riscv/li.c | 2 +-
> gcc/testsuite/gcc.target/riscv/load-immediate.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/losum-overflow.c | 2 +-
> gcc/testsuite/gcc.target/riscv/mcpu-6.c | 2 +-
> gcc/testsuite/gcc.target/riscv/mcpu-7.c | 2 +-
> gcc/testsuite/gcc.target/riscv/pr102957.c | 2 +-
> gcc/testsuite/gcc.target/riscv/pr103302.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/pr104140.c | 2 +-
> gcc/testsuite/gcc.target/riscv/pr84660.c | 2 +-
> gcc/testsuite/gcc.target/riscv/pr93202.c | 1 +
> gcc/testsuite/gcc.target/riscv/pr93304.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/pr95252.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/pr95683.c | 2 +-
> gcc/testsuite/gcc.target/riscv/pr98777.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/pr99702.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-1.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-10.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-11.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-12.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-13.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-14.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-15.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-16.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-2.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-3.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-4.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-5.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-6.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-7.c | 2 +-
> gcc/testsuite/gcc.target/riscv/predef-8.c | 2 +-
> gcc/testsuite/gcc.target/riscv/promote-type-for-libcall.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/riscv.exp | 4 +++-
> gcc/testsuite/gcc.target/riscv/save-restore-1.c | 2 +-
> gcc/testsuite/gcc.target/riscv/save-restore-2.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/save-restore-3.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/save-restore-4.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/save-restore-6.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/save-restore-7.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/save-restore-8.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/save-restore-9.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shift-and-1.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shift-and-2.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shift-shift-1.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shift-shift-2.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shift-shift-3.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shift-shift-4.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shift-shift-5.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/switch-qi.c | 2 +-
> gcc/testsuite/gcc.target/riscv/switch-si.c | 2 +-
> gcc/testsuite/gcc.target/riscv/weak-1.c | 2 +-
> gcc/testsuite/gcc.target/riscv/zba-adduw.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zba-slliuw.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zba-zextw.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c | 2 +-
> gcc/testsuite/gcc.target/riscv/zbb-min-max.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbbw.c | 2 +-
> gcc/testsuite/gcc.target/riscv/zbs-bclr.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbs-bext.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbs-binv.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zbs-bset.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zero-extend-1.c | 2 +-
> gcc/testsuite/gcc.target/riscv/zero-extend-2.c | 2 +-
> gcc/testsuite/gcc.target/riscv/zero-extend-3.c | 2 +-
> gcc/testsuite/gcc.target/riscv/zero-extend-4.c | 3 ++-
> gcc/testsuite/gcc.target/riscv/zero-extend-5.c | 2 +-
> 118 files changed, 168 insertions(+), 117 deletions(-)
>
> gcc-test-riscv-gcc-dg-runtest.diff
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-1.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -march=rv32i -march=rv32I -mabi=ilp32" } */
> +/* { dg-options "-march=rv32i -march=rv32I -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-10.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-10.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-10.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32gf2 -mabi=ilp32" } */
> +/* { dg-options "-march=rv32gf2 -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-11.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-11.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-11.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32g_zicsr2 -mabi=ilp32" } */
> +/* { dg-options "-march=rv32g_zicsr2 -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-12.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-12.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-12.c
> @@ -1,4 +1,4 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv64im1p2p3 -mabi=lp64" } */
> +/* { dg-options "-march=rv64im1p2p3 -mabi=lp64" } */
> int foo() {}
> /* { dg-error "'-march=rv64im1p2p3': for 'm1p2p\\?', version number with more than 2 level is not supported" "" { target *-*-* } 0 } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-2.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-2.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-2.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -march=rv32ixabc_xfoo -mabi=ilp32" } */
> +/* { dg-options "-march=rv32ixabc_xfoo -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-3.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-3.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-3.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -march=rv32isabc_xbar -mabi=ilp32" } */
> +/* { dg-options "-march=rv32isabc_xbar -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-4.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-4.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-4.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -march=rv32i2p3_m4p2 -mabi=ilp32" } */
> +/* { dg-options "-march=rv32i2p3_m4p2 -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-5.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-5.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-5.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -march=rv32isabc_hghi_zfoo_xbar -mabi=ilp32" } */
> +/* { dg-options "-march=rv32isabc_hghi_zfoo_xbar -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-6.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-6.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-6.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -march=rv32id -mabi=ilp32" } */
> +/* { dg-options "-march=rv32id -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-7.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-7.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-7.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32i -march=rv32im_s -mabi=ilp32" } */
> +/* { dg-options "-march=rv32i -march=rv32im_s -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-8.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-8.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-8.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -march=rv32id_zicsr_zifence -mabi=ilp32" } */
> +/* { dg-options "-march=rv32id_zicsr_zifence -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/arch-9.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/arch-9.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/arch-9.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32g2 -mabi=ilp32" } */
> +/* { dg-options "-march=rv32g2 -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-1.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute" } */
> +/* { dg-options "-mriscv-attribute" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-10.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-10.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-10.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32i -march=rv32im_sx_unexpectedstring -mabi=ilp32" } */
> +/* { dg-options "-march=rv32i -march=rv32im_sx_unexpectedstring -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-11.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-11.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-11.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32id -mabi=ilp32 -misa-spec=2.2" } */
> +/* { dg-options "-mriscv-attribute -march=rv32id -mabi=ilp32 -misa-spec=2.2" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-12.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-12.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-12.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32ifd -mabi=ilp32 -misa-spec=2.2" } */
> +/* { dg-options "-mriscv-attribute -march=rv32ifd -mabi=ilp32 -misa-spec=2.2" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-13.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-13.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-13.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32if3d -mabi=ilp32 -misa-spec=2.2" } */
> +/* { dg-options "-mriscv-attribute -march=rv32if3d -mabi=ilp32 -misa-spec=2.2" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-14.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-14.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-14.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32if -mabi=ilp32 -misa-spec=20190608" } */
> +/* { dg-options "-mriscv-attribute -march=rv32if -mabi=ilp32 -misa-spec=20190608" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-15.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-15.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-15.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=2.2" } */
> +/* { dg-options "-mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=2.2" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-16.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-16.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-16.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=20190608" } */
> +/* { dg-options "-mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=20190608" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-17.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-17.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-17.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=20191213" } */
> +/* { dg-options "-mriscv-attribute -march=rv32gc -mabi=ilp32 -misa-spec=20191213" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-2.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-2.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-2.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mno-riscv-attribute" } */
> +/* { dg-options "-mno-riscv-attribute" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-3.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-3.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-3.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -mpreferred-stack-boundary=8" } */
> +/* { dg-options "-mriscv-attribute -mpreferred-stack-boundary=8" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-4.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-4.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-4.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -mstrict-align" } */
> +/* { dg-options "-mriscv-attribute -mstrict-align" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-5.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-5.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-5.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -mno-strict-align" } */
> +/* { dg-options "-mriscv-attribute -mno-strict-align" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-7.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-7.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-7.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32e1p9 -mabi=ilp32e" } */
> +/* { dg-options "-mriscv-attribute -march=rv32e1p9 -mabi=ilp32e" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-8.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-8.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-8.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32i2p0xabc_xv5 -mabi=ilp32" } */
> +/* { dg-options "-mriscv-attribute -march=rv32i2p0xabc_xv5 -mabi=ilp32" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/attribute-9.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/attribute-9.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/attribute-9.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -mriscv-attribute -march=rv32i2p0sabc_xbar -mabi=ilp32e" } */
> +/* { dg-options "-mriscv-attribute -march=rv32i2p0sabc_xbar -mabi=ilp32e" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/interrupt-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/interrupt-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/interrupt-1.c
> @@ -1,6 +1,6 @@
> /* Verify the return instruction is mret. */
> /* { dg-do compile } */
> -/* { dg-options "-O" } */
> +/* { dg-options "" } */
> void __attribute__ ((interrupt))
> foo (void)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/interrupt-2.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/interrupt-2.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/interrupt-2.c
> @@ -1,6 +1,6 @@
> /* Verify that arg regs used as temporaries get saved. */
> /* { dg-do compile } */
> -/* { dg-options "-O" } */
> +/* { dg-options "" } */
> void __attribute__ ((interrupt))
> foo2 (void)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/interrupt-3.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/interrupt-3.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/interrupt-3.c
> @@ -1,6 +1,7 @@
> /* Verify t0 is saved before use. */
> /* { dg-do compile } */
> -/* { dg-options "-O0 -fomit-frame-pointer" } */
> +/* { dg-options "-fomit-frame-pointer" } */
> +/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */
> void __attribute__ ((interrupt))
> foo (void)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/interrupt-4.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/interrupt-4.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/interrupt-4.c
> @@ -1,6 +1,7 @@
> /* Verify t0 is saved before use. */
> /* { dg-do compile } */
> -/* { dg-options "-O0 -fomit-frame-pointer" } */
> +/* { dg-options "-fomit-frame-pointer" } */
> +/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */
> void __attribute__ ((interrupt))
> foo2 (void)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c
> @@ -1,6 +1,6 @@
> /* Verify proper errors are generated for conflicted interrupt type. */
> /* { dg-do compile } */
> -/* { dg-options "-O" } */
> +/* { dg-options "" } */
> void __attribute__ ((interrupt ("user")))
> foo(void);
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/interrupt-debug.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/interrupt-debug.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/interrupt-debug.c
> @@ -1,6 +1,7 @@
> /* Verify that we can compile with debug info. */
> /* { dg-do compile } */
> -/* { dg-options "-Og -g" } */
> +/* { dg-options "" } */
> +/* { dg-skip-if "" { *-*-* } { "*" } { "-g" } } */
> extern int var1;
> extern int var2;
> extern void sub2 (void);
> Index: gcc/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c
> @@ -1,6 +1,6 @@
> /* Verify the return instruction is mret. */
> /* { dg-do compile } */
> -/* { dg-options "-O" } */
> +/* { dg-options "" } */
> void __attribute__ ((interrupt ("machine")))
> foo (void)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/interrupt-smode.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/interrupt-smode.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/interrupt-smode.c
> @@ -1,6 +1,6 @@
> /* Verify the return instruction is mret. */
> /* { dg-do compile } */
> -/* { dg-options "-O" } */
> +/* { dg-options "" } */
> void __attribute__ ((interrupt ("supervisor")))
> foo (void)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/interrupt-umode.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/interrupt-umode.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/interrupt-umode.c
> @@ -1,6 +1,6 @@
> /* Verify the return instruction is mret. */
> /* { dg-do compile } */
> -/* { dg-options "-O" } */
> +/* { dg-options "" } */
> void __attribute__ ((interrupt ("user")))
> foo (void)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/li.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/li.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/li.c
> @@ -1,5 +1,5 @@
> /* { dg-do run } */
> -/* { dg-options "-O1" } */
> +/* { dg-options "" } */
> #include <stdlib.h>
> #define LOAD_IMM(var, val) \
> asm ("li %0, %1\n": "=r"(var): "i" (val))
> Index: gcc/gcc/testsuite/gcc.target/riscv/load-immediate.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/load-immediate.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/load-immediate.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* Check that we don't have unnecessary load immediate instructions. */
> void
> Index: gcc/gcc/testsuite/gcc.target/riscv/losum-overflow.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/losum-overflow.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/losum-overflow.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv32gc -mabi=ilp32 -O2 -fno-section-anchors" } */
> +/* { dg-options "-march=rv32gc -mabi=ilp32 -fno-section-anchors" } */
>
> /* Check for %lo overflow. Adding an offset larger than the alignment can
> overflow if the data is allocated to an address mod 4KB that is between
> Index: gcc/gcc/testsuite/gcc.target/riscv/mcpu-6.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/mcpu-6.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/mcpu-6.c
> @@ -1,6 +1,6 @@
> /* { dg-do compile } */
> /* Verify -mtune has higher priority than -mcpu for pipeline model . */
> -/* { dg-options "-mcpu=sifive-u74 -mtune=rocket -fdump-rtl-sched2-details -O3 -march=rv32i -mabi=ilp32" } */
> +/* { dg-options "-mcpu=sifive-u74 -mtune=rocket -fdump-rtl-sched2-details -march=rv32i -mabi=ilp32" } */
> /* { dg-final { scan-rtl-dump "simple_return\[ \]+:alu" "sched2" } } */
>
> int main()
> Index: gcc/gcc/testsuite/gcc.target/riscv/mcpu-7.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/mcpu-7.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/mcpu-7.c
> @@ -1,6 +1,6 @@
> /* { dg-do compile } */
> /* Verify -mtune has higher priority than -mcpu for pipeline model . */
> -/* { dg-options "-mcpu=sifive-s21 -mtune=sifive-u74 -fdump-rtl-sched2-details -O3 -march=rv32i -mabi=ilp32" } */
> +/* { dg-options "-mcpu=sifive-s21 -mtune=sifive-u74 -fdump-rtl-sched2-details -march=rv32i -mabi=ilp32" } */
> /* { dg-final { scan-rtl-dump "simple_return\[ \]+:sifive_7_B" "sched2" } } */
>
> int main()
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr102957.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr102957.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr102957.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O -march=rv64gzb -mabi=lp64" } */
> +/* { dg-options "-march=rv64gzb -mabi=lp64" } */
> int foo()
> {
> }
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr103302.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr103302.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr103302.c
> @@ -1,5 +1,6 @@
> /* { dg-do run { target int128 } } */
> -/* { dg-options "-Og -fharden-compares -fno-tree-dce -fno-tree-fre " } */
> +/* { dg-options "-fharden-compares -fno-tree-dce -fno-tree-fre" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> typedef unsigned char u8;
> typedef unsigned char __attribute__((__vector_size__ (32))) v256u8;
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr104140.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr104140.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr104140.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32im -mabi=ilp32" } */
> +/* { dg-options "-march=rv32im -mabi=ilp32" } */
> int x;
> unsigned u, v;
> void f (void)
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr84660.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr84660.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr84660.c
> @@ -1,5 +1,5 @@
> /* { dg-do run } */
> -/* { dg-options "-O2" } */
> +/* { dg-options "" } */
>
> extern void abort (void);
> extern void exit (int);
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr93202.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr93202.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr93202.c
> @@ -1,6 +1,7 @@
> /* PR inline-asm/93202 */
> /* { dg-do compile { target fpic } } */
> /* { dg-options "-fpic" } */
> +/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
>
> void
> foo (void)
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr93304.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr93304.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr93304.c
> @@ -1,7 +1,8 @@
> /* Verify the regrename won't rename registers to register which never used
> before. */
> /* { dg-do compile } */
> -/* { dg-options "-O -frename-registers" } */
> +/* { dg-options "-frename-registers" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> static unsigned _t = 0;
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr95252.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr95252.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr95252.c
> @@ -1,6 +1,7 @@
> /* PR target/95252 */
> -/* { dg-options "-O3 -funroll-loops -msave-restore" } */
> +/* { dg-options "-funroll-loops -msave-restore" } */
> /* { dg-do run } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> int a[6], b = 1, d, e;
> long long c;
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr95683.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr95683.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr95683.c
> @@ -1,5 +1,5 @@
> /* PR target/95683 */
> -/* { dg-options "-Os" } */
> +/* { dg-options "" } */
> /* { dg-do compile } */
> void a() {
> asm(""
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr98777.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr98777.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr98777.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-fstrict-aliasing -O" } */
> +/* { dg-options "-fstrict-aliasing" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> typedef struct {
> _Complex e;
> Index: gcc/gcc/testsuite/gcc.target/riscv/pr99702.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/pr99702.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/pr99702.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O" } */
> +/* { dg-options "" } */
> char n;
> void *i, *j;
> void foo(void) {
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-1.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32i -mabi=ilp32 -mcmodel=medlow" } */
> +/* { dg-options "-march=rv32i -mabi=ilp32 -mcmodel=medlow" } */
>
> int main () {
> #if !defined(__riscv)
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-10.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-10.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-10.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32i2p0 -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
> +/* { dg-options "-march=rv32i2p0 -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
>
> int main () {
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-11.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-11.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-11.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
>
> int main () {
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-12.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-12.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-12.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */
>
> int main () {
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-13.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-13.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-13.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32e -mabi=ilp32e -mcmodel=medlow -misa-spec=2.2" } */
> +/* { dg-options "-march=rv32e -mabi=ilp32e -mcmodel=medlow -misa-spec=2.2" } */
>
> int main () {
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-14.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-14.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-14.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32iv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
> +/* { dg-options "-march=rv32iv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */
>
> int main () {
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-15.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-15.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-15.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv64iv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
> +/* { dg-options "-march=rv64iv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
>
> int main () {
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-16.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-16.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-16.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv64i_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
> +/* { dg-options "-march=rv64i_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
>
> int main () {
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-2.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-2.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-2.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32imaf -mabi=ilp32f -mcmodel=medany" } */
> +/* { dg-options "-march=rv32imaf -mabi=ilp32f -mcmodel=medany" } */
>
> int main () {
> #if !defined(__riscv)
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-3.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-3.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-3.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32imafdc -mabi=ilp32d -fpic" } */
> +/* { dg-options "-march=rv32imafdc -mabi=ilp32d -fpic" } */
>
> int main () {
> #if !defined(__riscv)
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-4.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-4.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-4.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv64ia -mabi=lp64 -mcmodel=medlow" } */
> +/* { dg-options "-march=rv64ia -mabi=lp64 -mcmodel=medlow" } */
>
> int main () {
> #if !defined(__riscv)
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-5.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-5.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-5.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv64imf -mabi=lp64f -mcmodel=medany" } */
> +/* { dg-options "-march=rv64imf -mabi=lp64f -mcmodel=medany" } */
>
> int main () {
> #if !defined(__riscv)
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-6.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-6.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-6.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -fpic" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -fpic" } */
>
> int main () {
> #if !defined(__riscv)
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-7.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-7.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-7.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow" } */
> +/* { dg-options "-march=rv32em -mabi=ilp32e -mno-div -mcmodel=medlow" } */
>
> int main () {
> #if !defined(__riscv)
> Index: gcc/gcc/testsuite/gcc.target/riscv/predef-8.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/predef-8.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/predef-8.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -march=rv32if -mabi=ilp32f -mno-fdiv -mcmodel=medany" } */
> +/* { dg-options "-march=rv32if -mabi=ilp32f -mno-fdiv -mcmodel=medany" } */
>
> int main () {
> #if !defined(__riscv)
> Index: gcc/gcc/testsuite/gcc.target/riscv/promote-type-for-libcall.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/promote-type-for-libcall.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/promote-type-for-libcall.c
> @@ -1,5 +1,6 @@
> /* { dg-do run } */
> -/* { dg-options "-O1 -ftree-slp-vectorize -funroll-loops" } */
> +/* { dg-options "-ftree-slp-vectorize -funroll-loops" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> #include <stdio.h>
> #include <stdlib.h>
> Index: gcc/gcc/testsuite/gcc.target/riscv/riscv.exp
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/riscv.exp
> +++ gcc/gcc/testsuite/gcc.target/riscv/riscv.exp
> @@ -21,6 +21,8 @@ if ![istarget riscv*-*-*] then {
> return
> }
>
> +lappend ADDITIONAL_TORTURE_OPTIONS {-Og -g} {-Oz}
> +
> # Load support procs.
> load_lib gcc-dg.exp
>
> @@ -34,7 +36,7 @@ if ![info exists DEFAULT_CFLAGS] then {
> dg-init
>
> # Main loop.
> -dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
> +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
> "" $DEFAULT_CFLAGS
>
> # All done.
> Index: gcc/gcc/testsuite/gcc.target/riscv/save-restore-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/save-restore-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/save-restore-1.c
> @@ -1,5 +1,5 @@
> /* { dg-do run } */
> -/* { dg-options "-O2 -msave-restore -fomit-frame-pointer" } */
> +/* { dg-options "-msave-restore -fomit-frame-pointer" } */
>
> #include <stdlib.h>
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/save-restore-2.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/save-restore-2.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/save-restore-2.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -msave-restore" } */
> +/* { dg-options "-msave-restore" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* With -msave-restore in use it should not be possible to remove the calls
> to the save and restore stubs in this case (in current GCC). */
> Index: gcc/gcc/testsuite/gcc.target/riscv/save-restore-3.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/save-restore-3.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/save-restore-3.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -msave-restore" } */
> +/* { dg-options "-msave-restore" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
>
> /* With -msave-restore in use GCC should be able to remove the calls to the
> save and restore stubs in this case, replacing them with a tail call to
> Index: gcc/gcc/testsuite/gcc.target/riscv/save-restore-4.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/save-restore-4.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/save-restore-4.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -msave-restore" } */
> +/* { dg-options "-msave-restore" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
>
> /* This test covers a case where we can't (currently) remove the calls to
> the save/restore stubs. The cast of the return value from BAR requires
> Index: gcc/gcc/testsuite/gcc.target/riscv/save-restore-6.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/save-restore-6.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/save-restore-6.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -msave-restore" } */
> +/* { dg-options "-msave-restore" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* With -msave-restore in use GCC should be able to remove the calls to the
> save and restore stubs in this case, replacing them with a tail call to
> Index: gcc/gcc/testsuite/gcc.target/riscv/save-restore-7.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/save-restore-7.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/save-restore-7.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -msave-restore" } */
> +/* { dg-options "-msave-restore" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
>
> /* With -msave-restore in use it should not be possible to remove the calls
> to the save and restore stubs in this case (in current GCC). */
> Index: gcc/gcc/testsuite/gcc.target/riscv/save-restore-8.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/save-restore-8.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/save-restore-8.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -msave-restore" } */
> +/* { dg-options "-msave-restore" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* As a leaf function this should never have the calls to the save and
> restore stubs added, but lets check anyway. */
> Index: gcc/gcc/testsuite/gcc.target/riscv/save-restore-9.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/save-restore-9.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/save-restore-9.c
> @@ -1,5 +1,6 @@
> /* { dg-do run } */
> -/* { dg-options "-O2 -msave-restore" } */
> +/* { dg-options "-msave-restore" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> int
> __attribute__((noinline,noclone))
> Index: gcc/gcc/testsuite/gcc.target/riscv/shift-and-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shift-and-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shift-and-1.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv32gc -mabi=ilp32 -O" } */
> +/* { dg-options "-march=rv32gc -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* Test for <optab>si3_mask. */
> int
> Index: gcc/gcc/testsuite/gcc.target/riscv/shift-and-2.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shift-and-2.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shift-and-2.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile { target { riscv64*-*-* } } } */
> -/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* Test for <optab>si3_mask_1. */
> extern int k;
> Index: gcc/gcc/testsuite/gcc.target/riscv/shift-shift-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shift-shift-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shift-shift-1.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv32gc -mabi=ilp32 -O" } */
> +/* { dg-options "-march=rv32gc -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
>
> /* Test for lshrsi3_zero_extend_3+1 pattern that uses p2m1_shift_operand. */
> unsigned int
> Index: gcc/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
>
> /* Test for lshrsi3_zero_extend_3+1 pattern that uses p2m1_shift_operand. */
> unsigned int
> Index: gcc/gcc/testsuite/gcc.target/riscv/shift-shift-3.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shift-shift-3.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shift-shift-3.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
>
> /* Test for lshrsi3_zero_extend_3+2 pattern that uses
> high_mask_shift_operand. */
> Index: gcc/gcc/testsuite/gcc.target/riscv/shift-shift-4.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shift-shift-4.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shift-shift-4.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv32i -mabi=ilp32 -O2" } */
> +/* { dg-options "-march=rv32i -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
>
> /* One zero-extend shift can be eliminated by modifying the constant in the
> greater than test. Started working after modifying the splitter
> Index: gcc/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
>
> /* Fails if lshrsi3_zero_extend_3+1 uses a temp reg which has no REG_DEST
> note. */
> Index: gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
> +/* { dg-options "-march=rv32imc -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
>
> /* These stores cannot be compressed because x0 is not a compressed reg.
> Therefore the shorten_memrefs pass should not attempt to rewrite them into a
> Index: gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
> +/* { dg-options "-march=rv32imc -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
>
> /* shorten_memrefs should rewrite these load/stores into a compressible
> format. */
> Index: gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
> +/* { dg-options "-march=rv32imc -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
>
> /* These loads cannot be compressed because only one compressed reg is
> available (since args are passed in a0-a4, that leaves a5-a7 available, of
> Index: gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -march=rv64imc -mabi=lp64" } */
> +/* { dg-options "-march=rv64imc -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
>
> /* These stores cannot be compressed because x0 is not a compressed reg.
> Therefore the shorten_memrefs pass should not attempt to rewrite them into a
> Index: gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -march=rv64imc -mabi=lp64" } */
> +/* { dg-options "-march=rv64imc -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
>
> /* shorten_memrefs should rewrite these load/stores into a compressible
> format. */
> Index: gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -march=rv64imc -mabi=lp64" } */
> +/* { dg-options "-march=rv64imc -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
>
> /* These loads cannot be compressed because only one compressed reg is
> available (since args are passed in a0-a4, that leaves a5-a7 available, of
> Index: gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -march=rv32imc -mabi=ilp32 -mno-shorten-memrefs" } */
> +/* { dg-options "-march=rv32imc -mabi=ilp32 -mno-shorten-memrefs" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* Check that these load/stores do not get rewritten into a compressible format
> when shorten_memrefs is disabled. */
> Index: gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
> @@ -1,4 +1,5 @@
> -/* { dg-options "-Os -march=rv32imc -mabi=ilp32" } */
> +/* { dg-options "-march=rv32imc -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
>
> /* shorten_memrefs should use a correct base address*/
>
> Index: gcc/gcc/testsuite/gcc.target/riscv/switch-qi.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/switch-qi.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/switch-qi.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile { target { riscv64*-*-* } } } */
> -/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64" } */
>
> /* Test for riscv_extend_comparands patch. */
> extern void asdf(int);
> Index: gcc/gcc/testsuite/gcc.target/riscv/switch-si.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/switch-si.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/switch-si.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2" } */
> +/* { dg-options "" } */
>
> /* Test for do_tablejump patch. */
> extern void asdf(int);
> Index: gcc/gcc/testsuite/gcc.target/riscv/weak-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/weak-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/weak-1.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-mcmodel=medany -mexplicit-relocs -O" } */
> +/* { dg-options "-mcmodel=medany -mexplicit-relocs" } */
>
> /* Verify that the branch doesn't get optimized away. */
> extern int weak_func(void) __attribute__ ((weak));
> Index: gcc/gcc/testsuite/gcc.target/riscv/zba-adduw.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zba-adduw.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zba-adduw.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> int foo(int n, unsigned char *arr, unsigned y){
> int s = 0;
> Index: gcc/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> long test_1(long a, long b)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv32gc_zba -mabi=ilp32 -O2" } */
> +/* { dg-options "-march=rv32gc_zba -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> long test_1(long a, long b)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* RV64 only. */
> int foos(short *x, int n){
> Index: gcc/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" } } */
>
> long
> foo (long i)
> Index: gcc/gcc/testsuite/gcc.target/riscv/zba-zextw.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zba-zextw.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zba-zextw.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> long
> foo (long i)
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
>
> unsigned long long foo1(unsigned long long rs1, unsigned long long rs2)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
> +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
>
> unsigned int foo1(unsigned int rs1, unsigned int rs2)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
>
> long
> li_rori (void)
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-g" } } */
>
> long
> foo1 (long i, long j)
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */
>
> unsigned long foo1(unsigned long rs1, unsigned long rs2)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
> +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-g" } } */
>
> unsigned int foo1(unsigned int rs1, unsigned int rs2)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* RV64 only*/
> unsigned int rol(unsigned int rs1, unsigned int rs2)
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbbw.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbbw.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbbw.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
>
> int
> clz (int i)
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
>
> /* bclr */
> long
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbs-bext.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbs-bext.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbs-bext.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* bext */
> long
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbs-binv.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbs-binv.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbs-binv.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* binv */
> long
> Index: gcc/gcc/testsuite/gcc.target/riscv/zbs-bset.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zbs-bset.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zbs-bset.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
>
> /* bset */
> long
> Index: gcc/gcc/testsuite/gcc.target/riscv/zero-extend-1.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zero-extend-1.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zero-extend-1.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile { target { riscv64*-*-* } } } */
> -/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64" } */
> unsigned long
> sub1 (unsigned int i)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/zero-extend-2.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zero-extend-2.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zero-extend-2.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile { target { riscv64*-*-* } } } */
> -/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64" } */
> void
> sub (unsigned int wc, unsigned long step, unsigned char *start)
> {
> Index: gcc/gcc/testsuite/gcc.target/riscv/zero-extend-3.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zero-extend-3.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zero-extend-3.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile { target { riscv64*-*-* } } } */
> -/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64" } */
> extern int e (void);
> enum { a, b }
> c (void)
> Index: gcc/gcc/testsuite/gcc.target/riscv/zero-extend-4.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zero-extend-4.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zero-extend-4.c
> @@ -1,5 +1,6 @@
> /* { dg-do compile { target { riscv64*-*-* } } } */
> -/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
> int a, b, e;
> struct c *d;
> struct c
> Index: gcc/gcc/testsuite/gcc.target/riscv/zero-extend-5.c
> ===================================================================
> --- gcc.orig/gcc/testsuite/gcc.target/riscv/zero-extend-5.c
> +++ gcc/gcc/testsuite/gcc.target/riscv/zero-extend-5.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile { target { riscv64*-*-* } } } */
> -/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
> +/* { dg-options "-march=rv64gc -mabi=lp64" } */
> int
> sub (unsigned int i, unsigned int j, unsigned int k, int *array)
> {
next prev parent reply other threads:[~2022-02-07 16:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-31 23:04 Maciej W. Rozycki
2022-02-07 16:22 ` Kito Cheng [this message]
2022-02-08 12:24 ` Maciej W. Rozycki
2023-05-25 20:56 ` Thomas Schwinge
2023-05-25 21:17 ` Vineet Gupta
2023-05-25 21:20 ` Vineet Gupta
2023-05-26 0:06 ` Vineet Gupta
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