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References: <20221214080931.192028-1-juzhe.zhong@rivai.ai> <1bcbe6fb-74be-34b4-b178-ffb324abca43@gmail.com>
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From: Kito Cheng <kito.cheng@gmail.com>
Date: Mon, 19 Dec 2022 11:22:16 +0800
Message-ID: <CA+yXCZDOUHmTCkxhQeK1F82C6U6nSzNQB8isJc=ui5MGxS5J2g@mail.gmail.com>
Subject: Re: [PATCH] RISC-V: Add testcases for VSETVL PASS
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: =?UTF-8?B?6ZKf5bGF5ZOy?= <juzhe.zhong@rivai.ai>, 
	gcc-patches <gcc-patches@gcc.gnu.org>, palmer <palmer@dabbelt.com>
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Hi Jeff:

> Ah, I should have looked at those regexps closer.  Understood about the
> checking for hoisting the vsetvl.  Though it makes me wonder if we'd be
> better off dumping information out of the vsetvl pass.


I've discussed adding an extra verify pass and a kind of rating
mechnish to vsetvli pass with Ju-Zhe,
so that we don't need to do such asm scan, which is relatively fragile
to broken.

And we'll implement that in the next few weeks :)

Thanks