From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x935.google.com (mail-ua1-x935.google.com [IPv6:2607:f8b0:4864:20::935]) by sourceware.org (Postfix) with ESMTPS id 090503858C62 for ; Thu, 8 Jun 2023 13:24:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 090503858C62 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x935.google.com with SMTP id a1e0cc1a2514c-78a577f0747so234045241.0 for ; Thu, 08 Jun 2023 06:24:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686230681; x=1688822681; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=NH2RDg7gRoG0SsVo3aNLe9jor3xrtq83IHLn3DtSGKY=; b=pJqbHoH0XF9OCELfloNz+lx+9hcU86x++Q9xfe5E990w+OPjJkOpMV8txMEhtNX2RP ypC4uuxL4yBtmufqHrxcOYsVLpQ+g83vxb4SRBQHvny4BBbIh0031/yQN+gL0kwgc3Oq S2b6p4403sTa7yKT8YSUb1ppL9Ka5MZIW3Glwe4V2KR1GnI18s8IKd6Ha8WwrXMuuEgC sreALmPnX55tbpBIVMn9BMrYZikuB9C5PtYogJ2y/l1w7+Jrg0tlZb/GvNxkRQE6hEqm Ah0vwCZrYI3p9anrnAv4DKggeAAnJpJB2mNvZdlcQTm3wAMLnF16uwXsehhe8iuadOMX yeNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686230681; x=1688822681; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NH2RDg7gRoG0SsVo3aNLe9jor3xrtq83IHLn3DtSGKY=; b=BXxDExtKBxNlwSTPHF2Z/FJ4qgaOLNeqtHp7O9OAkwRJ5H83iL1qgGhQupoqEq24kW tGXWrXNFF+nl4z0iTJzw2PxkkySFChhsEm1bpj2Yd376TLbaglHTFTvBxF20iqTGZf77 KJS7fcBUrCJRaoLOVV8NwBvmnny4FTnax4Ge+55C7b/ZPKlegbDWBDy/ifq1QcIXklBn juLQBjkxZxq8d8fZavCM0Xxany8GR5yWhB6JP0Wq3XAEalMQZT+R2X97m4bF4L1Bm6TI 1sOZLkeoMsVnqIP7MyK+cfWq6V1Kd1TLPgPXsDCBM+1I20WK0tJnCF2p3f+rRlLk7rqa ZQYA== X-Gm-Message-State: AC+VfDx+8yiMdGkPuhI2WlQsqoaA7D6YnhO+0EW9DHqW5bpy2iK9ShvM XEv9y1VVp0x3qauiMw9QK041Fu7S1QJrxeyzxVs= X-Google-Smtp-Source: ACHHUZ7a4rq4VWmIRsU36z8bYMj8CKM5p27QWr4dkNtYARCrWDPT03/vQpyetFXoxCI/FtAUbMwQavbw6GAUXkgT+gY= X-Received: by 2002:a67:e9da:0:b0:43b:29a2:f5ee with SMTP id q26-20020a67e9da000000b0043b29a2f5eemr2313791vso.17.1686230680836; Thu, 08 Jun 2023 06:24:40 -0700 (PDT) MIME-Version: 1.0 References: <20230606123646.1553843-1-pan2.li@intel.com> <20230608062954.2513718-1-pan2.li@intel.com> <16ACB62752DD1A1D+20230608163204553687136@rivai.ai> In-Reply-To: From: Kito Cheng Date: Thu, 8 Jun 2023 21:24:29 +0800 Message-ID: Subject: Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. To: "Li, Pan2" Cc: "juzhe.zhong@rivai.ai" , gcc-patches , Robin Dapp , jeffreyalaw , "Wang, Yanzhang" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,FREEMAIL_REPLY,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: I like JuZhe's proposal too since it's a less invasive way :) On Thu, Jun 8, 2023 at 9:18=E2=80=AFPM Li, Pan2 via Gcc-patches wrote: > > Thanks Juzhe for the idea. It looks work well as we expected, with the fo= llowing try. > > > 1. Allow all FP=3D16 types for vfadd, then _zvfh and _zvfhmin will be = OK. > 2. Add restriction define_attr as juzhe mentioned, then _zvfh works we= ll, and _zvfhmin will meet error like unsatisfied insn. > > I think only we need to do is the define_attr, and there will be no chang= es to vector.md. If no more concern, will have a try for this approach. > > Pan > > From: juzhe.zhong@rivai.ai > Sent: Thursday, June 8, 2023 4:32 PM > To: kito.cheng > Cc: Li, Pan2 ; gcc-patches ; = Robin Dapp ; jeffreyalaw ; Wang= , Yanzhang > Subject: Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFH= MIN. > > I have an idea base on what Kito said. > We enable vfadd FP16 for TARGET_ZVFH. But we don't need to add TARGET_VEC= TOR && > for each instruction. > > We can reference riscv.md: > (define_attr "ext_enabled" "no,yes" > (cond [(eq_attr "ext" "base") > (const_string "yes") > > (and (eq_attr "ext" "f") > (match_test "TARGET_HARD_FLOAT")) > (const_string "yes") > > (and (eq_attr "ext" "d") > (match_test "TARGET_DOUBLE_FLOAT")) > (const_string "yes") > > (and (eq_attr "ext" "vector") > (match_test "TARGET_VECTOR")) > (const_string "yes") > ] > (const_string "no"))) > > Define a new attribute as follows: > (define_attr "fp16_vector_enabled" "no,yes" > (cond [ > (and (eq_attr "type" "vfalu") > (and eq_attr "mode" "VNx1HF") > (match_test "!TARGET_ZVFH"))) > (const_string "no") > ] > (const_string "yes"))) > > > I think you can do experiment with this to see whether it can disable MD = pattern. > > ________________________________ > juzhe.zhong@rivai.ai > > From: Kito Cheng > Date: 2023-06-08 15:58 > To: juzhe.zhong@rivai.ai > CC: pan2.li; gcc-patches; Robin Dapp; jeffreyalaw; yanzhang.wang > Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. > I am thinking, is it possible to use mode attr to remove the overhead > of checking the mode for other FP modes other than FP16? > > e.g. > (define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [ > (VNx1HF "TARGET_ZVFH") > ... > (VNx1SF "1") > ... > ]) > > > "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > -> > "TARGET_VECTOR && " > > > On Thu, Jun 8, 2023 at 2:35=E2=80=AFPM juzhe.zhong@rivai.ai > > wrote: > > > > LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP1= 6 autovec. > > > > > > > > juzhe.zhong@rivai.ai > > > > From: pan2.li > > Date: 2023-06-08 14:29 > > To: gcc-patches > > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.c= heng > > Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. > > From: Pan Li > > > > > This patch would like to refactor the requirement of both the ZVFH > > and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the > > iterators of RVV. And then the ZVFH will leverage one function as > > the gate for FP16 supported or not. > > > > Please note the ZVFH will cover the ZVFHMIN instructions. This patch > > add one test for this. > > > > Signed-off-by: Pan Li > > > Co-Authored by: Juzhe-Zhong > > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-protos.h (float_mode_supported_p): > > New function to float point is supported by extension. > > * config/riscv/riscv-v.cc (float_mode_supported_p): > > Ditto. > > * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT. > > * config/riscv/vector.md: Add condition to FP define insn. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test > > for ZVFHMIN. > > --- > > gcc/config/riscv/riscv-protos.h | 1 + > > gcc/config/riscv/riscv-v.cc | 12 ++ > > gcc/config/riscv/vector-iterators.md | 23 +-- > > gcc/config/riscv/vector.md | 144 ++++++++++-------- > > .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +- > > 5 files changed, 118 insertions(+), 77 deletions(-) > > > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-p= rotos.h > > index ebbaac255f9..1f606f59ce1 100644 > > --- a/gcc/config/riscv/riscv-protos.h > > +++ b/gcc/config/riscv/riscv-protos.h > > @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx); > > bool check_builtin_call (location_t, vec, unsigned int, > > tree, unsigned int, tree *); > > bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); > > +bool float_mode_supported_p (machine_mode mode); > > bool legitimize_move (rtx, rtx); > > void emit_vlmax_vsetvl (machine_mode, rtx); > > void emit_hard_vlmax_vsetvl (machine_mode, rtx); > > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > > index 49752cd8899..fe4eb058ec0 100644 > > --- a/gcc/config/riscv/riscv-v.cc > > +++ b/gcc/config/riscv/riscv-v.cc > > @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_IN= T minval, > > && IN_RANGE (INTVAL (elt), minval, maxval)); > > } > > +/* Return true if the inner of mode is HFmode when ZVFH enabled, or ot= her > > + float point machine mode. */ > > +bool > > +float_mode_supported_p (machine_mode mode) > > +{ > > + machine_mode inner_mode =3D GET_MODE_INNER (mode); > > + > > + gcc_assert (FLOAT_MODE_P (inner_mode)); > > + > > + return inner_mode =3D=3D HFmode ? TARGET_ZVFH : true; > > +} > > + > > /* Return true if VEC is a constant in which every element is in the ra= nge > > [MINVAL, MAXVAL]. The elements do not need to have the same value. > > diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/ve= ctor-iterators.md > > index f4946d84449..234b712bc9d 100644 > > --- a/gcc/config/riscv/vector-iterators.md > > +++ b/gcc/config/riscv/vector-iterators.md > > @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [ > > (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "T= ARGET_VECTOR_ELEN_64") > > (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (V= Nx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >=3D 128") > > - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") > > - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") > > - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") > > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN =3D=3D 32") > > + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN =3D=3D 64") > > (VNx8HF "TARGET_VECTOR_ELEN_FP_16") > > (VNx16HF "TARGET_VECTOR_ELEN_FP_16") > > (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > > @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [ > > (define_mode_iterator V_FRACT [ > > (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 3= 2") (VNx8QI "TARGET_MIN_VLEN >=3D 128") > > (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VN= x4HI "TARGET_MIN_VLEN >=3D 128") > > - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VN= x4HF "TARGET_MIN_VLEN >=3D 128") > > + > > + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") > > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > > + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >=3D 128") > > + > > (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TA= RGET_MIN_VLEN >=3D 128") > > (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_= MIN_VLEN < 128") > > (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >=3D 128") > > @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [ > > ]) > > (define_mode_iterator VWEXTF [ > > - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") > > - (VNx2SF "TARGET_VECTOR_ELEN_FP_32") > > - (VNx4SF "TARGET_VECTOR_ELEN_FP_32") > > - (VNx8SF "TARGET_VECTOR_ELEN_FP_32") > > - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > > - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >=3D 128") > > + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TAR= GET_MIN_VLEN < 128") > > + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") > > + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") > > + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") > > + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TA= RGET_MIN_VLEN > 32") > > + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TA= RGET_MIN_VLEN >=3D 128") > > (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") > > (VNx2DF "TARGET_VECTOR_ELEN_FP_64") > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > > index 1d1847bd85a..2fe0233f102 100644 > > --- a/gcc/config/riscv/vector.md > > +++ b/gcc/config/riscv/vector.md > > @@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast" > > (vec_duplicate:VF > > (match_operand: 3 "direct_broadcast_operand" " f, f,Wdm= ,Wdm,Wdm,Wdm, f, f")) > > (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu= , 0, vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "@ > > vfmv.v.f\t%0,%3 > > vfmv.v.f\t%0,%3 > > @@ -5685,7 +5685,7 @@ (define_insn "@pred_>" > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") > > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vf.vv\t%0,%3,%4%p1" > > [(set_attr "type" "") > > (set_attr "mode" "")]) > > @@ -5705,7 +5705,7 @@ (define_insn "@pred_" > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") > > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vf.vv\t%0,%3,%4%p1" > > [(set_attr "type" "") > > (set_attr "mode" "")]) > > @@ -5728,7 +5728,7 @@ (define_insn "@pred__scalar" > > (match_operand: 4 "register_operand" " f, f, f, f")) > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vf.vf\t%0,%3,%4%p1" > > [(set_attr "type" "") > > (set_attr "mode" "")]) > > @@ -5749,7 +5749,7 @@ (define_insn "@pred__scalar" > > (match_operand: 4 "register_operand" " f, f, f, f")) > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vf.vf\t%0,%3,%4%p1" > > [(set_attr "type" "") > > (set_attr "mode" "")]) > > @@ -5772,7 +5772,7 @@ (define_insn "@pred__scalar" > > (vec_duplicate:VF > > (match_operand: 4 "register_operand" " f, f, f, f"))) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vf.vf\t%0,%3,%4%p1" > > [(set_attr "type" "") > > (set_attr "mode" "")]) > > @@ -5795,7 +5795,7 @@ (define_insn "@pred__reverse_scalar" > > (match_operand: 4 "register_operand" " f, f, f, f")) > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfr.vf\t%0,%3,%4%p1" > > [(set_attr "type" "") > > (set_attr "mode" "")]) > > @@ -5815,7 +5815,7 @@ (define_insn "@pred_" > > [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr") > > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] V= COPYSIGNS) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfsgnj.vv\t%0,%3,%4%p1" > > [(set_attr "type" "vfsgnj") > > (set_attr "mode" "")]) > > @@ -5836,7 +5836,7 @@ (define_insn "@pred__scalar" > > (vec_duplicate:VF > > (match_operand: 4 "register_operand" " f, f, f, f"))] V= COPYSIGNS) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfsgnj.vf\t%0,%3,%4%p1" > > [(set_attr "type" "vfsgnj") > > (set_attr "mode" "")]) > > @@ -5894,7 +5894,7 @@ (define_insn "*pred_" > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")= ) > > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")= ) > > (match_dup 2)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "@ > > vf.vv\t%0,%3,%4%p1 > > vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1 > > @@ -5927,7 +5927,7 @@ (define_insn "*pred_" > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")= ) > > (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")= ) > > (match_dup 4)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "@ > > vf.vv\t%0,%2,%3%p1 > > vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 > > @@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_= " > > (match_operand:VF 3 "register_operand" " vr, vr")) > > (match_operand:VF 4 "vector_arith_operand" " vr, vr")) > > (match_operand:VF 5 "register_operand" " 0, vr")))] > > - "TARGET_VECTOR > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode) > > && !rtx_equal_p (operands[2], operands[5]) > > && !rtx_equal_p (operands[3], operands[5]) > > && !rtx_equal_p (operands[4], operands[5])" > > @@ -6021,7 +6021,7 @@ (define_insn "*pred__scalar" > > (match_operand:VF 3 "register_operand" " 0, vr, 0, vr"= )) > > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr"= )) > > (match_dup 3)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "@ > > vf.vf\t%0,%2,%4%p1 > > vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1 > > @@ -6055,7 +6055,7 @@ (define_insn "*pred__scalar" > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"= )) > > (match_operand:VF 4 "register_operand" " 0, vr, 0, vr"= )) > > (match_dup 4)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "@ > > vf.vf\t%0,%2,%3%p1 > > vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 > > @@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul_= _scalar" > > (match_operand:VF 3 "register_operand" " vr, vr")) > > (match_operand:VF 4 "vector_arith_operand" " vr, vr")) > > (match_operand:VF 5 "register_operand" " 0, vr")))] > > - "TARGET_VECTOR > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode) > > && !rtx_equal_p (operands[3], operands[5]) > > && !rtx_equal_p (operands[4], operands[5])" > > "@ > > @@ -6154,7 +6154,7 @@ (define_insn "*pred_" > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")= )) > > (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")= ) > > (match_dup 2)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "@ > > vf.vv\t%0,%3,%4%p1 > > vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1 > > @@ -6188,7 +6188,7 @@ (define_insn "*pred_" > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")= )) > > (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")= ) > > (match_dup 4)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "@ > > vf.vv\t%0,%2,%3%p1 > > vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 > > @@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_" > > (match_operand:VF 3 "register_operand" " vr, vr"))) > > (match_operand:VF 4 "vector_arith_operand" " vr, vr")) > > (match_operand:VF 5 "register_operand" " 0, vr")))] > > - "TARGET_VECTOR > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode) > > && !rtx_equal_p (operands[2], operands[5]) > > && !rtx_equal_p (operands[3], operands[5]) > > && !rtx_equal_p (operands[4], operands[5])" > > @@ -6285,7 +6285,7 @@ (define_insn "*pred__scalar" > > (match_operand:VF 3 "register_operand" " 0, vr, 0, v= r"))) > > (match_operand:VF 4 "register_operand" " vr, vr, vr, v= r")) > > (match_dup 3)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "@ > > vf.vf\t%0,%2,%4%p1 > > vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1 > > @@ -6320,7 +6320,7 @@ (define_insn "*pred__scalar" > > (match_operand:VF 3 "register_operand" " vr, vr, vr, v= r"))) > > (match_operand:VF 4 "register_operand" " 0, vr, 0, v= r")) > > (match_dup 4)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "@ > > vf.vf\t%0,%2,%3%p1 > > vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 > > @@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg__scalar" > > (match_operand:VF 3 "register_operand" " vr, vr"))) > > (match_operand:VF 4 "vector_arith_operand" " vr, vr")) > > (match_operand:VF 5 "register_operand" " 0, vr")))] > > - "TARGET_VECTOR > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode) > > && !rtx_equal_p (operands[3], operands[5]) > > && !rtx_equal_p (operands[4], operands[5])" > > "@ > > @@ -6399,7 +6399,7 @@ (define_insn "@pred_" > > (any_float_unop:VF > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vf.v\t%0,%3%p1" > > [(set_attr "type" "") > > (set_attr "mode" "") > > @@ -6422,7 +6422,7 @@ (define_insn "@pred_" > > (any_float_unop_nofrm:VF > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vf.v\t%0,%3%p1" > > [(set_attr "type" "") > > (set_attr "mode" "") > > @@ -6445,7 +6445,7 @@ (define_insn "@pred_" > > (unspec:VF > > [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] V= FMISC) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vf.v\t%0,%3%p1" > > [(set_attr "type" "") > > (set_attr "mode" "")]) > > @@ -6464,7 +6464,7 @@ (define_insn "@pred_class" > > (unspec: > > [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")= ] UNSPEC_VFCLASS) > > (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")= ))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfclass.v\t%0,%3%p1" > > [(set_attr "type" "vfclass") > > (set_attr "mode" "")]) > > @@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_" > > (float_extend:VWEXTF > > (match_operand: 4 "register_operand" " vr, vr= "))) > > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0= ")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfw.vv\t%0,%3,%4%p1" > > [(set_attr "type" "vf") > > (set_attr "mode" "")]) > > @@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen__scal= ar" > > (vec_duplicate: > > (match_operand: 4 "register_operand" " f, f")))) > > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0= ")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfw.vf\t%0,%3,%4%p1" > > [(set_attr "type" "vf") > > (set_attr "mode" "")]) > > @@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_" > > (float_extend:VWEXTF > > (match_operand: 4 "register_operand" " vr, vr= "))) > > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0= ")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfw.wv\t%0,%3,%4%p1" > > [(set_attr "type" "vf") > > (set_attr "mode" "")]) > > @@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen__scalar" > > (vec_duplicate: > > (match_operand: 4 "register_operand" " f, f")))) > > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0= ")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfw.wf\t%0,%3,%4%p1" > > [(set_attr "type" "vf") > > (set_attr "mode" "")]) > > @@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_" > > (match_operand: 4 "register_operand" " vr"))) > > (match_operand:VWEXTF 2 "register_operand" " 0")) > > (match_dup 2)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfw.vv\t%0,%3,%4%p1" > > [(set_attr "type" "vfwmuladd") > > (set_attr "mode" "")]) > > @@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul__scala= r" > > (match_operand: 4 "register_operand" " vr"))) > > (match_operand:VWEXTF 2 "register_operand" " 0")) > > (match_dup 2)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfw.vf\t%0,%3,%4%p1" > > [(set_attr "type" "vfwmuladd") > > (set_attr "mode" "")]) > > @@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_" > > (match_operand: 4 "register_operand" " vr")= ))) > > (match_operand:VWEXTF 2 "register_operand" " 0")= ) > > (match_dup 2)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfw.vv\t%0,%3,%4%p1" > > [(set_attr "type" "vfwmuladd") > > (set_attr "mode" "")]) > > @@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg__s= calar" > > (match_operand: 4 "register_operand" " vr")= ))) > > (match_operand:VWEXTF 2 "register_operand" " 0")= ) > > (match_dup 2)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfw.vf\t%0,%3,%4%p1" > > [(set_attr "type" "vfwmuladd") > > (set_attr "mode" "")]) > > @@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp" > > [(match_operand:VF 4 "register_operand" " vr, vr") > > (match_operand:VF 5 "register_operand" " vr, vr")]) > > (match_operand: 2 "vector_merge_operand" " vu, 0")))] > > - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR)" > > + "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR) > > + && riscv_vector::float_mode_supported_p (mode)" > > "vmf%B3.vv\t%0,%4,%5%p1" > > [(set_attr "type" "vfcmp") > > (set_attr "mode" "")]) > > @@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp_narrow_merge_tie_ma= sk" > > [(match_operand:VF 3 "register_operand" " vr") > > (match_operand:VF 4 "register_operand" " vr")]) > > (match_dup 1)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vmf%B2.vv\t%0,%3,%4,v0.t" > > [(set_attr "type" "vfcmp") > > (set_attr "mode" "") > > @@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp_narrow" > > [(match_operand:VF 4 "register_operand" " vr, 0, v= r, 0, 0, vr, 0, vr, vr") > > (match_operand:VF 5 "register_operand" " vr, vr, = 0, 0, vr, 0, 0, vr, vr")]) > > (match_operand: 2 "vector_merge_operand" " vu, vu, v= u, vu, 0, 0, 0, vu, 0")))] > > - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR)" > > + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR) > > + && riscv_vector::float_mode_supported_p (mode)" > > "vmf%B3.vv\t%0,%4,%5%p1" > > [(set_attr "type" "vfcmp") > > (set_attr "mode" "")]) > > @@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_ma= sk" > > (vec_duplicate:VF > > (match_operand: 4 "register_operand" " f"))]) > > (match_dup 1)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vmf%B2.vf\t%0,%3,%4,v0.t" > > [(set_attr "type" "vfcmp") > > (set_attr "mode" "") > > @@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp_scalar" > > (vec_duplicate:VF > > (match_operand: 5 "register_operand" " f, f"))]) > > (match_operand: 2 "vector_merge_operand" " vu, 0")))] > > - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR)" > > + "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR) > > + && riscv_vector::float_mode_supported_p (mode)" > > "vmf%B3.vf\t%0,%4,%5%p1" > > [(set_attr "type" "vfcmp") > > (set_attr "mode" "")]) > > @@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp_scalar_narrow" > > (vec_duplicate:VF > > (match_operand: 5 "register_operand" " f, f, = f, f, f"))]) > > (match_operand: 2 "vector_merge_operand" " vu, vu, = 0, vu, 0")))] > > - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR)" > > + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR) > > + && riscv_vector::float_mode_supported_p (mode)" > > "vmf%B3.vf\t%0,%4,%5%p1" > > [(set_attr "type" "vfcmp") > > (set_attr "mode" "")]) > > @@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne_scalar_merge_tie_m= ask" > > (match_operand: 4 "register_operand" " f")) > > (match_operand:VF 3 "register_operand" " vr")]) > > (match_dup 1)))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vmf%B2.vf\t%0,%3,%4,v0.t" > > [(set_attr "type" "vfcmp") > > (set_attr "mode" "") > > @@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne_scalar" > > (match_operand: 5 "register_operand" " f, f")) > > (match_operand:VF 4 "register_operand" " vr, vr")]) > > (match_operand: 2 "vector_merge_operand" " vu, 0")))] > > - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR)" > > + "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR) > > + && riscv_vector::float_mode_supported_p (mode)" > > "vmf%B3.vf\t%0,%4,%5%p1" > > [(set_attr "type" "vfcmp") > > (set_attr "mode" "")]) > > @@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne_scalar_narrow" > > (match_operand: 5 "register_operand" " f, f, = f, f, f")) > > (match_operand:VF 4 "register_operand" " vr, 0, = 0, vr, vr")]) > > (match_operand: 2 "vector_merge_operand" " vu, vu, = 0, vu, 0")))] > > - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR)" > > + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RI= SCV_VECTOR) > > + && riscv_vector::float_mode_supported_p (mode)" > > "vmf%B3.vf\t%0,%4,%5%p1" > > [(set_attr "type" "vfcmp") > > (set_attr "mode" "")]) > > @@ -6966,7 +6972,7 @@ (define_insn "@pred_merge_scalar" > > (match_operand:VF 2 "register_operand" " vr,vr") > > (match_operand: 4 "register_operand" " vm,vm")) > > (match_operand:VF 1 "vector_merge_operand" " vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfmerge.vfm\t%0,%2,%3,%4" > > [(set_attr "type" "vfmerge") > > (set_attr "mode" "")]) > > @@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x_f" > > (unspec: > > [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")= ] VFCVTS) > > (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")= ))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfcvt.x.f.v\t%0,%3%p1" > > [(set_attr "type" "vfcvtftoi") > > (set_attr "mode" "")]) > > @@ -7013,7 +7019,7 @@ (define_insn "@pred_" > > (any_fix: > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")= ) > > (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")= ))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfcvt.rtz.x.f.v\t%0,%3%p1" > > [(set_attr "type" "vfcvtftoi") > > (set_attr "mode" "")]) > > @@ -7034,7 +7040,7 @@ (define_insn "@pred_" > > (any_float:VF > > (match_operand: 3 "register_operand" " vr, vr, vr, vr")) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0"))= )] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfcvt.f.x.v\t%0,%3%p1" > > [(set_attr "type" "vfcvtitof") > > (set_attr "mode" "")]) > > @@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x_f" > > (unspec:VWCONVERTI > > [(match_operand: 3 "register_operand" " vr, vr")] V= FCVTS) > > (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (m= ode)" > > "vfwcvt.x.f.v\t%0,%3%p1" > > [(set_attr "type" "vfwcvtftoi") > > (set_attr "mode" "")]) > > @@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_" > > (any_fix:VWCONVERTI > > (match_operand: 3 "register_operand" " vr, vr")) > > (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (m= ode)" > > "vfwcvt.rtz.x.f.v\t%0,%3%p1" > > [(set_attr "type" "vfwcvtftoi") > > (set_attr "mode" "")]) > > @@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_" > > (any_float:VF > > (match_operand: 3 "register_operand" " vr, vr")) > > (match_operand:VF 2 "vector_merge_operand" " vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfwcvt.f.x.v\t%0,%3%p1" > > [(set_attr "type" "vfwcvtitof") > > (set_attr "mode" "")]) > > @@ -7119,7 +7125,7 @@ (define_insn "@pred_extend" > > (float_extend:VWEXTF > > (match_operand: 3 "register_operand" " vr, vr"= )) > > (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0"= )))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfwcvt.f.f.v\t%0,%3%p1" > > [(set_attr "type" "vfwcvtftof") > > (set_attr "mode" "")]) > > @@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x_f" > > (unspec: > > [(match_operand:VF 3 "register_operand" " 0, 0, 0, 0= , vr, vr")] VFCVTS) > > (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0= , vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfncvt.x.f.w\t%0,%3%p1" > > [(set_attr "type" "vfncvtftoi") > > (set_attr "mode" "")]) > > @@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_" > > (any_fix: > > (match_operand:VF 3 "register_operand" " 0, 0, 0, 0,= vr, vr")) > > (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0,= vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (m= ode)" > > "vfncvt.rtz.x.f.w\t%0,%3%p1" > > [(set_attr "type" "vfncvtftoi") > > (set_attr "mode" "")]) > > @@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_" > > (any_float: > > (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0,= vr, vr")) > > (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0,= vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (m= ode)" > > "vfncvt.f.x.w\t%0,%3%p1" > > [(set_attr "type" "vfncvtitof") > > (set_attr "mode" "")]) > > @@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc" > > (float_truncate: > > (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0= , 0, vr, vr")) > > (match_operand: 2 "vector_merge_operand" " vu, 0, vu= , 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfncvt.f.f.w\t%0,%3%p1" > > [(set_attr "type" "vfncvtftof") > > (set_attr "mode" "")]) > > @@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc" > > [(float_truncate: > > (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0= , 0, vr, vr"))] UNSPEC_ROD) > > (match_operand: 2 "vector_merge_operand" " vu, 0, vu= , 0, vu, 0")))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfncvt.rod.f.f.w\t%0,%3%p1" > > [(set_attr "type" "vfncvtftof") > > (set_attr "mode" "")]) > > @@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_" > > (parallel [(const_int 0)]))) > > (match_operand:VF 3 "register_operand" " vr, vr")) > > (match_operand: 2 "vector_merge_operand" " vu, 0")] U= NSPEC_REDUC))] > > - "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128" > > + "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128 > > + && riscv_vector::float_mode_supported_p (mode)" > > "vfred.vs\t%0,%3,%4%p1" > > [(set_attr "type" "vfredu") > > (set_attr "mode" "")]) > > @@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_" > > (parallel [(const_int 0)]))) > > (match_operand:VF_ZVE64 3 "register_operand" " vr, v= r")) > > (match_operand: 2 "vector_merge_operand" " vu, = 0")] UNSPEC_REDUC))] > > - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64" > > + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64 > > + && riscv_vector::float_mode_supported_p (mode)" > > "vfred.vs\t%0,%3,%4%p1" > > [(set_attr "type" "vfredu") > > (set_attr "mode" "")]) > > @@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_" > > (parallel [(const_int 0)]))) > > (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, v= r, vr")) > > (match_operand: 2 "vector_merge_operand" " vu, 0, v= u, 0")] UNSPEC_REDUC))] > > - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 32" > > + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 32 > > + && riscv_vector::float_mode_supported_p (mode)" > > "vfred.vs\t%0,%3,%4%p1" > > [(set_attr "type" "vfredu") > > (set_attr "mode" "")]) > > @@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus" > > (parallel [(const_int 0)]))) > > (match_operand:VF 3 "register_operand" " vr, vr")) > > (match_operand: 2 "vector_merge_operand" " vu, 0")]= UNSPEC_REDUC)] ORDER))] > > - "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128" > > + "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128 > > + && riscv_vector::float_mode_supported_p (mode)" > > "vfredsum.vs\t%0,%3,%4%p1" > > [(set_attr "type" "vfred") > > (set_attr "mode" "")]) > > @@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus" > > (parallel [(const_int 0)]))) > > (match_operand:VF_ZVE64 3 "register_operand" " vr, = vr")) > > (match_operand: 2 "vector_merge_operand" " vu, = 0")] UNSPEC_REDUC)] ORDER))] > > - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64" > > + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64 > > + && riscv_vector::float_mode_supported_p (mode)" > > "vfredsum.vs\t%0,%3,%4%p1" > > [(set_attr "type" "vfred") > > (set_attr "mode" "")]) > > @@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus" > > (parallel [(const_int 0)]))) > > (match_operand:VF_ZVE32 3 "register_operand" " vr, vr,= vr, vr")) > > (match_operand: 2 "vector_merge_operand" " vu, 0,= vu, 0")] UNSPEC_REDUC)] ORDER))] > > - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 32" > > + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 32 > > + && riscv_vector::float_mode_supported_p (mode)" > > "vfredsum.vs\t%0,%3,%4%p1" > > [(set_attr "type" "vfred") > > (set_attr "mode" "")]) > > @@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus= " > > (match_operand:VWF 3 "register_operand" " vr, vr") > > (match_operand: 4 "register_operand" " vr, vr") > > (match_operand: 2 "vector_merge_operand" " vu, 0")= ] UNSPEC_WREDUC_SUM)] ORDER))] > > - "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128" > > + "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128 > > + && riscv_vector::float_mode_supported_p (mode)" > > "vfwredsum.vs\t%0,%3,%4%p1" > > [(set_attr "type" "vfwred") > > (set_attr "mode" "")]) > > @@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus= " > > (match_operand:VWF_ZVE64 3 "register_operand" " vr, = vr") > > (match_operand: 4 "register_operand" " vr, = vr") > > (match_operand: 2 "vector_merge_operand" " vu, = 0")] UNSPEC_WREDUC_SUM)] ORDER))] > > - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64" > > + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64 > > + && riscv_vector::float_mode_supported_p (mode)" > > "vfwredsum.vs\t%0,%3,%4%p1" > > [(set_attr "type" "vfwred") > > (set_attr "mode" "")]) > > @@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first" > > (match_operand:VF 1 "register_operand" "vr") > > (parallel [(const_int 0)])) > > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfmv.f.s\t%0,%1" > > [(set_attr "type" "vfmovvf") > > (set_attr "mode" "")]) > > @@ -7778,7 +7792,7 @@ (define_insn "@pred_slide" > > (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0") > > (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") > > (match_operand: 4 "register_operand" " f, f, f, f")] V= FSLIDES1))] > > - "TARGET_VECTOR" > > + "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" > > "vfslide.vf\t%0,%3,%4%p1" > > [(set_attr "type" "vfslide") > > (set_attr "mode" "")]) > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.= c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > > index 0923b6bc4d2..f1a29b639e0 100644 > > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > > @@ -3,6 +3,8 @@ > > #include "riscv_vector.h" > > +typedef _Float16 float16_t; > > + > > vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) { > > return __riscv_vfncvt_f_f_w_f16mf4(src, vl); > > } > > @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t s= rc, size_t vl) { > > return __riscv_vfwcvt_f_f_v_f32m8(src, vl); > > } > > -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e= 16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */ > > +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) { > > + return __riscv_vle16_v_f16mf4(base, vl); > > +} > > + > > +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) { > > + return __riscv_vle16_v_f16m8(base, vl); > > +} > > + > > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e= 16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */ > > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e1= 6,\s*mf2,\s*t[au],\s*m[au]} 2 } } */ > > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e1= 6,\s*m1,\s*t[au],\s*m[au]} 2 } } */ > > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e1= 6,\s*m2,\s*t[au],\s*m[au]} 2 } } */ > > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e1= 6,\s*m4,\s*t[au],\s*m[au]} 2 } } */ > > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e= 16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ > > /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-= 9]+} 5 } } */ > > /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-= 9]+} 5 } } */ > > - > > +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]= +\)} 4 } } */ > > -- > > 2.34.1 > > > > >