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Rozycki" Cc: gcc-patches@gcc.gnu.org, Andrew Waterman , Jim Wilson , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_ASCII_DIVIDERS,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Sun, Nov 19, 2023 at 1:38=E2=80=AFPM Maciej W. Rozycki wrote: > > Verify, for Ventana and Zicond targets and the GEU and LEU > conditional-move operations, that if-conversion triggers via > `noce_try_cmove' at `-mbranch-cost=3D4' setting, which makes branchless > code sequences produced by if-conversion cheaper than their original > branched equivalents, and that extraneous instructions such as SEQZ, > etc. are not present in output. > > gcc/testsuite/ > * gcc.target/riscv/movdigtu-ventana.c: New test. > * gcc.target/riscv/movdigtu-zicond.c: New test. > * gcc.target/riscv/movdiltu-ventana.c: New test. > * gcc.target/riscv/movdiltu-zicond.c: New test. > * gcc.target/riscv/movsigtu-ventana.c: New test. > * gcc.target/riscv/movsigtu-zicond.c: New test. > * gcc.target/riscv/movsiltu-ventana.c: New test. > * gcc.target/riscv/movsiltu-zicond.c: New test. > --- > gcc/testsuite/gcc.target/riscv/movdigtu-ventana.c | 28 +++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdigtu-zicond.c | 28 +++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdiltu-ventana.c | 28 +++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movdiltu-zicond.c | 28 +++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsigtu-ventana.c | 28 +++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsigtu-zicond.c | 28 +++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsiltu-ventana.c | 28 +++++++++++++++= +++++++ > gcc/testsuite/gcc.target/riscv/movsiltu-zicond.c | 28 +++++++++++++++= +++++++ > 8 files changed, 224 insertions(+) > > gcc-riscv-expand-conditional-move-geu-leu-test-movcc.diff > Index: gcc/gcc/testsuite/gcc.target/riscv/movdigtu-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdigtu-ventana.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D4 -fdump-rtl-ce1" } */ > + > +typedef unsigned int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdigtu (int_t w, int_t x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branchless assembly like: > + > + sgtu a1,a0,a1 > + vt.maskcn a3,a3,a1 > + vt.maskc a1,a2,a1 > + or a0,a1,a3 > + */ > + > +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." = 1 "ce1" } } */ > +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noc= e_try_cmove" 1 "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } *= / > Index: gcc/gcc/testsuite/gcc.target/riscv/movdigtu-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdigtu-zicond.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 4 -fdump-rtl-ce1" } */ > + > +typedef unsigned int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdigtu (int_t w, int_t x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branchless assembly like: > + > + sgtu a1,a0,a1 > + czero.nez a3,a3,a1 > + czero.eqz a1,a2,a1 > + or a0,a1,a3 > + */ > + > +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." = 1 "ce1" } } */ > +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noc= e_try_cmove" 1 "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } *= / > Index: gcc/gcc/testsuite/gcc.target/riscv/movdiltu-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdiltu-ventana.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D4 -fdump-rtl-ce1" } */ > + > +typedef unsigned int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdiltu (int_t w, int_t x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branchless assembly like: > + > + sltu a1,a0,a1 > + vt.maskcn a3,a3,a1 > + vt.maskc a1,a2,a1 > + or a0,a1,a3 > + */ > + > +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." = 1 "ce1" } } */ > +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noc= e_try_cmove" 1 "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } *= / > Index: gcc/gcc/testsuite/gcc.target/riscv/movdiltu-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movdiltu-zicond.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 4 -fdump-rtl-ce1" } */ > + > +typedef unsigned int __attribute__ ((mode (DI))) int_t; > + > +int_t > +movdiltu (int_t w, int_t x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branchless assembly like: > + > + sltu a1,a0,a1 > + czero.nez a3,a3,a1 > + czero.eqz a1,a2,a1 > + or a0,a1,a3 > + */ > + > +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." = 1 "ce1" } } */ > +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noc= e_try_cmove" 1 "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } *= / > Index: gcc/gcc/testsuite/gcc.target/riscv/movsigtu-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsigtu-ventana.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D4 -fdump-rtl-ce1" } */ > + > +typedef unsigned int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsigtu (int_t w, int_t x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branchless assembly like: > + > + sgtu a1,a0,a1 > + vt.maskcn a3,a3,a1 > + vt.maskc a1,a2,a1 > + or a0,a1,a3 > + */ > + > +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." = 1 "ce1" } } */ > +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noc= e_try_cmove" 1 "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } *= / > Index: gcc/gcc/testsuite/gcc.target/riscv/movsigtu-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsigtu-zicond.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 4 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=3Drv32gc_zicond -mtune=3Drocket -mbranch-cost=3D= 4 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef unsigned int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsigtu (int_t w, int_t x, int_t y, int_t z) > +{ > + return w > x ? y : z; > +} > + > +/* Expect branchless assembly like: > + > + sgtu a1,a0,a1 > + czero.nez a3,a3,a1 > + czero.eqz a1,a2,a1 > + or a0,a1,a3 > + */ > + > +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." = 1 "ce1" } } */ > +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noc= e_try_cmove" 1 "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } *= / > Index: gcc/gcc/testsuite/gcc.target/riscv/movsiltu-ventana.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsiltu-ventana.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_xventanacondops -mtune=3Drocket -mbranc= h-cost=3D4 -fdump-rtl-ce1" } */ > + > +typedef unsigned int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsiltu (int_t w, int_t x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branchless assembly like: > + > + sltu a1,a0,a1 > + vt.maskcn a3,a3,a1 > + vt.maskc a1,a2,a1 > + or a0,a1,a3 > + */ > + > +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." = 1 "ce1" } } */ > +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noc= e_try_cmove" 1 "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } *= / > Index: gcc/gcc/testsuite/gcc.target/riscv/movsiltu-zicond.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- /dev/null > +++ gcc/gcc/testsuite/gcc.target/riscv/movsiltu-zicond.c > @@ -0,0 +1,28 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > +/* { dg-options "-march=3Drv64gc_zicond -mtune=3Drocket -mbranch-cost=3D= 4 -fdump-rtl-ce1" { target { rv64 } } } */ > +/* { dg-options "-march=3Drv32gc_zicond -mtune=3Drocket -mbranch-cost=3D= 4 -fdump-rtl-ce1" { target { rv32 } } } */ > + > +typedef unsigned int __attribute__ ((mode (SI))) int_t; > + > +int_t > +movsiltu (int_t w, int_t x, int_t y, int_t z) > +{ > + return w < x ? y : z; > +} > + > +/* Expect branchless assembly like: > + > + sltu a1,a0,a1 > + czero.nez a3,a3,a1 > + czero.eqz a1,a2,a1 > + or a0,a1,a3 > + */ > + > +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." = 1 "ce1" } } */ > +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noc= e_try_cmove" 1 "ce1" } } */ > +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ > +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ > +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ > +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } *= /