From: Kito Cheng <kito.cheng@gmail.com>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
gcc-patches@gcc.gnu.org, palmer@dabbelt.com,
rdapp@ventanamicro.com, juzhe.zhong@rivai.ai
Subject: Re: [PATCH v2 4/4] RISC-V: Implement target attribute
Date: Wed, 11 Oct 2023 14:29:10 -0700 [thread overview]
Message-ID: <CA+yXCZDUdQa2Nn0c_7VG0gN8ubC1C-EkAj2Z-8kuFn8dJn_UJw@mail.gmail.com> (raw)
In-Reply-To: <3bc0c5c9-2ea8-4f57-ba72-f8505f3665c1@gmail.com>
> Assuming you're agreeable to adjusting the code to avoid alloca, we'll
> do a quick turnaround on the v3 -- I'll just audit the return paths to
> make sure we don't leak and we'll be good to go.
Thanks for point out that, let me figure out which is the best way to
fix that, using xstrdup + free or some other smart pointer from C++ :P
next prev parent reply other threads:[~2023-10-11 21:29 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-10 4:13 [PATCH v2 0/4] RISC-V " Kito Cheng
2023-10-10 4:13 ` [PATCH v2 1/4] options: Define TARGET_<NAME>_P and TARGET_<NAME>_OPTS_P macro for Mask and InverseMask Kito Cheng
2023-10-10 13:50 ` Jeff Law
2023-10-11 21:20 ` Kito Cheng
2023-10-11 22:49 ` 钟居哲
2023-10-11 22:50 ` Kito Cheng
2023-10-11 23:23 ` Kito Cheng
2023-10-10 4:13 ` [PATCH v2 2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC] Kito Cheng
2023-10-10 13:51 ` Jeff Law
2023-10-11 21:21 ` Kito Cheng
2023-10-10 4:13 ` [PATCH v2 3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support Kito Cheng
2023-10-10 14:00 ` Jeff Law
2023-10-11 21:19 ` Kito Cheng
2023-10-10 4:13 ` [PATCH v2 4/4] RISC-V: Implement target attribute Kito Cheng
2023-10-10 15:24 ` Jeff Law
2023-10-11 21:29 ` Kito Cheng [this message]
2023-10-10 9:56 ` [PATCH v2 0/4] RISC-V " juzhe.zhong
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