From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe34.google.com (mail-vs1-xe34.google.com [IPv6:2607:f8b0:4864:20::e34]) by sourceware.org (Postfix) with ESMTPS id 3CFE03858D33 for ; Thu, 11 May 2023 11:09:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3CFE03858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe34.google.com with SMTP id ada2fe7eead31-43470e2f643so2870794137.3 for ; Thu, 11 May 2023 04:09:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683803360; x=1686395360; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=x++9HgIwi8RTKUrJNssSRt/6v+AKkkQt8UbVoaY6+Qg=; b=pZSA0pZBk3iJLHdOH4VtgY2dxfotVnML3AdHrUFuJ2nK3FHh72U/ymAYfLRiaHlRwI aFZjYL5nQZ/TXoKFvoKtw3u08RzUFzxId2sEwJEs3efsBNYCEp+9YDpjJlGJ5sSWun4y reyGvr0zleSkriOUf36rMngt9i1KKjIxLKwWhbceUVfTLJQuZ0Emwk12FBf22y55DcYQ b+CcA+oNGTUAuutm3ED5uDqvotkV99Oanto3FiQWJv3txiHd5Uk8cBK38X+jXfVzg3i0 CzyC2LNLAWaGUkXoAn6MQWb7Xgr7ZenmvaJ2+ZZAweCeuuQlpyvkqvy9/PE0WJJ982Gm Ijdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683803360; x=1686395360; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=x++9HgIwi8RTKUrJNssSRt/6v+AKkkQt8UbVoaY6+Qg=; b=P+C5ejcULoiqjXNPcpjPGIH0yEdZeOiIu55cVujGIajWIidtVabwJI5/kiC1Vg81Wp 2Fcext83CqNIlZYwbwcrWrVm4qrt1GuuoQvcduslwp7I9LK1AMB2SqkAVACn6EK4UtuD 9ClomxbyqQJhslT+Je36pyKxefaFhDoG6i6nCfB25MOolnnlUFCQc+MkNho8VTIDdDYu mPfNUfYsRHWKYjFrW07DfRHeylVJv/ZiU9dbjRR33EY73vXjlDU1RNcuLodRyXeOYo8V e3l+q3Zo8avTu3kB9aocd+wB3vyinCVYirtFhYyldnuhq228mYO0bk+6s208SHgxzGYX epIw== X-Gm-Message-State: AC+VfDxEIJLBkLWkjWWwh2+TT5Rcf0u8B+SWCGPxyfvKovXLokbteX57 3fI3wyz04WOL+tVvPKMYjVylgnUOXYJkpv0OY9w= X-Google-Smtp-Source: ACHHUZ4Y4A0wdJNUNETRCjO7mxOc7gef77a3jlKZpzzfBxUJ0Fs55YVkxC4tPKgfyZlREkUevaQxfCyE2BPATcuGPNc= X-Received: by 2002:a05:6102:3a66:b0:42c:7d66:659 with SMTP id bf6-20020a0561023a6600b0042c7d660659mr7478552vsb.23.1683803360157; Thu, 11 May 2023 04:09:20 -0700 (PDT) MIME-Version: 1.0 References: <2d3b5b57-cc1c-aee1-ea70-99a3fae02dff@gmail.com> <97E521C18AB53297+20230511183512155164218@rivai.ai> In-Reply-To: <97E521C18AB53297+20230511183512155164218@rivai.ai> From: Kito Cheng Date: Thu, 11 May 2023 19:09:07 +0800 Message-ID: Subject: Re: [PATCH v2] RISC-V: Add autovectorization tests for binary integer, operations. To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: Robin Dapp , palmer , gcc-patches , collison , jeffreyalaw Content-Type: multipart/alternative; boundary="00000000000027641105fb69059f" X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000027641105fb69059f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LGTM juzhe.zhong@rivai.ai =E6=96=BC 2023=E5=B9=B45=E6=9C= =8811=E6=97=A5 =E9=80=B1=E5=9B=9B 18:36 =E5=AF=AB=E9=81=93=EF=BC=9A > LGTM. Plz commit it now. Then I can rebase vec_init patch. > > > > juzhe.zhong@rivai.ai > > From: Robin Dapp > Date: 2023-05-11 18:27 > To: Kito Cheng; Palmer Dabbelt > CC: gcc-patches; juzhe.zhong; collison; jeffreyalaw > Subject: [PATCH v2] RISC-V: Add autovectorization tests for binary > integer, operations. > Changes from v1: > > - Split into run tests (guarded by riscv_vector) and compile tests > which will be executed unconditionally. Doing dg-do run and -save-tem= ps > on a non-supported target will not do anything at all. > > This patchs adds scan as well as execution tests for vectorized > binary integer operations. The tests are not comprehensive as > the vector type promotions (vec_unpack, extend etc.) are not implemented > yet. Also, vmulh, vmulhu, and vmulhsu and others are still missing. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/shift-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/shift-template.h: New test. > * gcc.target/riscv/rvv/autovec/shift-run.c: New test. > * gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/shift-scalar-template.h: New test. > * gcc.target/riscv/rvv/autovec/shift-scalar-run.c: New test. > * gcc.target/riscv/rvv/autovec/vadd-run-template.h: New test. > * gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vadd-template.h: New test. > * gcc.target/riscv/rvv/autovec/vand-run.c: New test. > * gcc.target/riscv/rvv/autovec/vand-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vand-template.h: New test. > * gcc.target/riscv/rvv/autovec/vdiv-run.c: New test. > * gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vdiv-template.h: New test. > * gcc.target/riscv/rvv/autovec/vmax-run.c: New test. > * gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vmax-template.h: New test. > * gcc.target/riscv/rvv/autovec/vmin-run.c: New test. > * gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vmin-template.h: New test. > * gcc.target/riscv/rvv/autovec/vmul-run.c: New test. > * gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vmul-template.h: New test. > * gcc.target/riscv/rvv/autovec/vor-run.c: New test. > * gcc.target/riscv/rvv/autovec/vor-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vor-template.h: New test. > * gcc.target/riscv/rvv/autovec/vrem-run.c: New test. > * gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vrem-template.h: New test. > * gcc.target/riscv/rvv/autovec/vsub-run.c: New test. > * gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vsub-template.h: New test. > * gcc.target/riscv/rvv/autovec/vxor-run.c: New test. > * gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: New test. > * gcc.target/riscv/rvv/autovec/vxor-template.h: New test. > > Co-authored-by: Michael Collison > --- > .../riscv/rvv/autovec/shift-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/shift-run.c | 52 ++++++++ > .../riscv/rvv/autovec/shift-rv32gcv.c | 11 ++ > .../riscv/rvv/autovec/shift-rv64gcv.c | 11 ++ > .../riscv/rvv/autovec/shift-scalar-run.c | 4 + > .../riscv/rvv/autovec/shift-scalar-rv32gcv.c | 7 ++ > .../riscv/rvv/autovec/shift-scalar-rv64gcv.c | 7 ++ > .../riscv/rvv/autovec/shift-scalar-template.h | 119 ++++++++++++++++++ > .../riscv/rvv/autovec/shift-template.h | 34 +++++ > .../riscv/rvv/autovec/vadd-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vadd-run.c | 69 ++++++++++ > .../riscv/rvv/autovec/vadd-rv32gcv.c | 7 ++ > .../riscv/rvv/autovec/vadd-rv64gcv.c | 7 ++ > .../riscv/rvv/autovec/vadd-template.h | 56 +++++++++ > .../riscv/rvv/autovec/vand-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vand-run.c | 69 ++++++++++ > .../riscv/rvv/autovec/vand-rv32gcv.c | 7 ++ > .../riscv/rvv/autovec/vand-rv64gcv.c | 7 ++ > .../riscv/rvv/autovec/vand-template.h | 56 +++++++++ > .../riscv/rvv/autovec/vdiv-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vdiv-run.c | 47 +++++++ > .../riscv/rvv/autovec/vdiv-rv32gcv.c | 9 ++ > .../riscv/rvv/autovec/vdiv-rv64gcv.c | 9 ++ > .../riscv/rvv/autovec/vdiv-template.h | 34 +++++ > .../riscv/rvv/autovec/vmax-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vmax-run.c | 47 +++++++ > .../riscv/rvv/autovec/vmax-rv32gcv.c | 7 ++ > .../riscv/rvv/autovec/vmax-rv64gcv.c | 7 ++ > .../riscv/rvv/autovec/vmax-template.h | 34 +++++ > .../riscv/rvv/autovec/vmin-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vmin-run.c | 47 +++++++ > .../riscv/rvv/autovec/vmin-rv32gcv.c | 7 ++ > .../riscv/rvv/autovec/vmin-rv64gcv.c | 7 ++ > .../riscv/rvv/autovec/vmin-template.h | 34 +++++ > .../riscv/rvv/autovec/vmul-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vmul-run.c | 47 +++++++ > .../riscv/rvv/autovec/vmul-rv32gcv.c | 6 + > .../riscv/rvv/autovec/vmul-rv64gcv.c | 6 + > .../riscv/rvv/autovec/vmul-template.h | 34 +++++ > .../riscv/rvv/autovec/vor-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vor-run.c | 69 ++++++++++ > .../riscv/rvv/autovec/vor-rv32gcv.c | 7 ++ > .../riscv/rvv/autovec/vor-rv64gcv.c | 7 ++ > .../riscv/rvv/autovec/vor-template.h | 56 +++++++++ > .../riscv/rvv/autovec/vrem-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vrem-run.c | 47 +++++++ > .../riscv/rvv/autovec/vrem-rv32gcv.c | 9 ++ > .../riscv/rvv/autovec/vrem-rv64gcv.c | 9 ++ > .../riscv/rvv/autovec/vrem-template.h | 34 +++++ > .../riscv/rvv/autovec/vsub-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vsub-run.c | 47 +++++++ > .../riscv/rvv/autovec/vsub-rv32gcv.c | 6 + > .../riscv/rvv/autovec/vsub-rv64gcv.c | 6 + > .../riscv/rvv/autovec/vsub-template.h | 34 +++++ > .../riscv/rvv/autovec/vxor-run-template.h | 0 > .../gcc.target/riscv/rvv/autovec/vxor-run.c | 69 ++++++++++ > .../riscv/rvv/autovec/vxor-rv32gcv.c | 7 ++ > .../riscv/rvv/autovec/vxor-rv64gcv.c | 7 ++ > .../riscv/rvv/autovec/vxor-template.h | 56 +++++++++ > 59 files changed, 1375 insertions(+) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv= .c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv= .c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run-template.h > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h > > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c > new file mode 100644 > index 00000000000..67e9f8ca242 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c > @@ -0,0 +1,52 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "shift-template.h" > + > +#include > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D VAL; \ > + b##TYPE[i] =3D i % 4; \ > + } \ > + vshl_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D (VAL << (i % 4))); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + TYPE bs##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + as##TYPE[i] =3D VAL; \ > + bs##TYPE[i] =3D i % 4; \ > + } \ > + vshiftr_##TYPE (as##TYPE, as##TYPE, bs##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D (VAL >> (i % 4))); > + > +#define RUN_ALL() \ > + RUN(int16_t, 1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, 3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, 5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c > new file mode 100644 > index 00000000000..da0f79a1cf0 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "shift-template.h" > + > +/* TODO: For int16_t and uint16_t we need widening/promotion patterns. > + Therefore, expect only 4 vsll.vv instead of 6 for now. */ > + > +/* { dg-final { scan-assembler-times {\tvsll\.vv} 4 } } */ > +/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */ > +/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c > new file mode 100644 > index 00000000000..aba9c842b1d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "shift-template.h" > + > +/* TODO: For int16_t and uint16_t we need widening/promotion patterns. > + Therefore, expect only 4 vsll.vv instead of 6 for now. */ > + > +/* { dg-final { scan-assembler-times {\tvsll\.vv} 4 } } */ > +/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */ > +/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c > new file mode 100644 > index 00000000000..1e801743cf9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c > @@ -0,0 +1,4 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "shift-scalar-template.h" > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c > new file mode 100644 > index 00000000000..8850d389c3a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "shift-scalar-template.h" > + > +/* { dg-final { scan-assembler-times {\tvsll\.vi} 31 } } */ > +/* { dg-final { scan-assembler-times {\tvsll\.vx} 1 } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c > new file mode 100644 > index 00000000000..aabd2e03231 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "shift-scalar-template.h" > + > +/* { dg-final { scan-assembler-times {\tvsll\.vi} 31 } } */ > +/* { dg-final { scan-assembler-times {\tvsll\.vx} 1 } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h > new file mode 100644 > index 00000000000..a0ddc00849d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h > @@ -0,0 +1,119 @@ > +/* Test shifts by scalar (immediate or register) amount. */ > +/* { dg-do run } */ > +/* { dg-additional-options "-std=3Dc99 > --param=3Driscv-autovec-preference=3Dscalable -fno-vect-cost-model > --save-temps" } */ > + > +#include > +#include > + > +#define SHIFTL(TYPE,VAL) \ > + __attribute__ ((noipa)) \ > + void vsll_##TYPE_##VAL (TYPE *dst, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] <<=3D VAL; \ > + } > + > +#define SHIFTR(TYPE,VAL) \ > + __attribute__ ((noipa)) \ > + void vsrx_##TYPE_##VAL (TYPE *dst, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] >>=3D VAL; \ > + } > + > +#define TEST_ALL() \ > +SHIFTL(uint32_t,1) \ > +SHIFTL(uint32_t,2) \ > +SHIFTL(uint32_t,3) \ > +SHIFTL(uint32_t,4) \ > +SHIFTL(uint32_t,5) \ > +SHIFTL(uint32_t,6) \ > +SHIFTL(uint32_t,7) \ > +SHIFTL(uint32_t,8) \ > +SHIFTL(uint32_t,9) \ > +SHIFTL(uint32_t,10) \ > +SHIFTL(uint32_t,11) \ > +SHIFTL(uint32_t,12) \ > +SHIFTL(uint32_t,13) \ > +SHIFTL(uint32_t,14) \ > +SHIFTL(uint32_t,15) \ > +SHIFTL(uint32_t,16) \ > +SHIFTL(uint32_t,17) \ > +SHIFTL(uint32_t,18) \ > +SHIFTL(uint32_t,19) \ > +SHIFTL(uint32_t,20) \ > +SHIFTL(uint32_t,21) \ > +SHIFTL(uint32_t,22) \ > +SHIFTL(uint32_t,23) \ > +SHIFTL(uint32_t,24) \ > +SHIFTL(uint32_t,25) \ > +SHIFTL(uint32_t,26) \ > +SHIFTL(uint32_t,27) \ > +SHIFTL(uint32_t,28) \ > +SHIFTL(uint32_t,29) \ > +SHIFTL(uint32_t,30) \ > +SHIFTL(uint64_t,31) \ > + > +TEST_ALL() > + > +#define SZ 32 > + > +#define TEST_VSLL(TYPE,VAL) \ > + TYPE a##TYPE##VAL[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + a##TYPE##VAL[i] =3D 2; \ > + vsll_##TYPE_##VAL (a##TYPE##VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE##VAL[i] =3D=3D (2ll << VAL)); > + > +__attribute__((noipa)) > +void vsllvx (uint32_t *dst, int val, int n) > +{ > + for (int i =3D 0; i < n; i++) > + dst[i] <<=3D val; > +} > + > +#define TEST_VSLLVX \ > + uint32_t a[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + a[i] =3D 2; \ > + vsllvx (a, 17, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a[i] =3D=3D (2 << 17)); > + > +int main () > +{ > + TEST_VSLL(uint32_t,1) > + TEST_VSLL(uint32_t,2) > + TEST_VSLL(uint32_t,3) > + TEST_VSLL(uint32_t,4) > + TEST_VSLL(uint32_t,5) > + TEST_VSLL(uint32_t,6) > + TEST_VSLL(uint32_t,7) > + TEST_VSLL(uint32_t,8) > + TEST_VSLL(uint32_t,9) > + TEST_VSLL(uint32_t,10) > + TEST_VSLL(uint32_t,11) > + TEST_VSLL(uint32_t,12) > + TEST_VSLL(uint32_t,13) > + TEST_VSLL(uint32_t,14) > + TEST_VSLL(uint32_t,15) > + TEST_VSLL(uint32_t,16) > + TEST_VSLL(uint32_t,17) > + TEST_VSLL(uint32_t,18) > + TEST_VSLL(uint32_t,19) > + TEST_VSLL(uint32_t,20) > + TEST_VSLL(uint32_t,21) > + TEST_VSLL(uint32_t,22) > + TEST_VSLL(uint32_t,23) > + TEST_VSLL(uint32_t,24) > + TEST_VSLL(uint32_t,25) > + TEST_VSLL(uint32_t,26) > + TEST_VSLL(uint32_t,27) > + TEST_VSLL(uint32_t,28) > + TEST_VSLL(uint32_t,29) > + TEST_VSLL(uint32_t,30) > + TEST_VSLL(uint64_t,31) > + > + TEST_VSLLVX > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h > new file mode 100644 > index 00000000000..64e0a386b06 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h > @@ -0,0 +1,34 @@ > +#include > + > +#define TEST1_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vshl_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] << b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vshiftr_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] >> b[i]; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST1_TYPE(int16_t) \ > + TEST1_TYPE(uint16_t) \ > + TEST1_TYPE(int32_t) \ > + TEST1_TYPE(uint32_t) \ > + TEST1_TYPE(int64_t) \ > + TEST1_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) > + > +TEST_ALL() > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run.c > new file mode 100644 > index 00000000000..8bdc7a220c3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run.c > @@ -0,0 +1,69 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vadd-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D 0; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D VAL); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D 0; \ > + vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D VAL); > + > +#define RUN3(TYPE,VAL) \ > + TYPE ai##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + ai##TYPE[i] =3D VAL; \ > + vaddi_##TYPE (ai##TYPE, ai##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (ai##TYPE[i] =3D=3D VAL + 15); > + > +#define RUN3M(TYPE,VAL) \ > + TYPE aim##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + aim##TYPE[i] =3D VAL; \ > + vaddim_##TYPE (aim##TYPE, aim##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (aim##TYPE[i] =3D=3D VAL - 16); > + > +#define RUN_ALL() \ > + RUN(int16_t, -1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, -3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, -5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) \ > + RUN3M(int16_t, 13) \ > + RUN3(uint16_t, 14) \ > + RUN3M(int32_t, 15) \ > + RUN3(uint32_t, 16) \ > + RUN3M(int64_t, 17) \ > + RUN3(uint64_t, 18) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c > new file mode 100644 > index 00000000000..799ed27ec6d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vadd-template.h" > + > +/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */ > +/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c > new file mode 100644 > index 00000000000..d9ba5a385b9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vadd-template.h" > + > +/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */ > +/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h > new file mode 100644 > index 00000000000..5ed79329138 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h > @@ -0,0 +1,56 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] + b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] + b; \ > + } > + > +#define TEST3_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vaddi_##TYPE (TYPE *dst, TYPE *a, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] + 15; \ > + } > + > +#define TEST3M_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vaddim_##TYPE (TYPE *dst, TYPE *a, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] - 16; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) \ > + TEST3M_TYPE(int16_t) \ > + TEST3_TYPE(uint16_t) \ > + TEST3M_TYPE(int32_t) \ > + TEST3_TYPE(uint32_t) \ > + TEST3M_TYPE(int64_t) \ > + TEST3_TYPE(uint64_t) > + > +TEST_ALL() > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c > new file mode 100644 > index 00000000000..1c7def563ac > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c > @@ -0,0 +1,69 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vand-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D 123; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vand_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D (TYPE)(123 & VAL)); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D 123; \ > + vands_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D (123 & VAL)); > + > +#define RUN3(TYPE,VAL) \ > + TYPE ai##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + ai##TYPE[i] =3D VAL; \ > + vandi_##TYPE (ai##TYPE, ai##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (ai##TYPE[i] =3D=3D (VAL & 15)); > + > +#define RUN3M(TYPE,VAL) \ > + TYPE aim##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + aim##TYPE[i] =3D VAL; \ > + vandim_##TYPE (aim##TYPE, aim##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (aim##TYPE[i] =3D=3D (VAL & -16)); > + > +#define RUN_ALL() \ > + RUN(int16_t, -1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, -3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, -5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) \ > + RUN3M(int16_t, 13) \ > + RUN3(uint16_t, 14) \ > + RUN3M(int32_t, 15) \ > + RUN3(uint32_t, 16) \ > + RUN3M(int64_t, 17) \ > + RUN3(uint64_t, 18) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c > new file mode 100644 > index 00000000000..24fc70b4ea4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vand-template.h" > + > +/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */ > +/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c > new file mode 100644 > index 00000000000..3cd766b95a3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vand-template.h" > + > +/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */ > +/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h > new file mode 100644 > index 00000000000..7d02c83d164 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h > @@ -0,0 +1,56 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] & b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vands_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] & b; \ > + } > + > +#define TEST3_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vandi_##TYPE (TYPE *dst, TYPE *a, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] & 15; \ > + } > + > +#define TEST3M_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vandim_##TYPE (TYPE *dst, TYPE *a, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] & -16; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) \ > + TEST3M_TYPE(int16_t) \ > + TEST3_TYPE(uint16_t) \ > + TEST3M_TYPE(int32_t) \ > + TEST3_TYPE(uint32_t) \ > + TEST3M_TYPE(int64_t) \ > + TEST3_TYPE(uint64_t) > + > +TEST_ALL() > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c > new file mode 100644 > index 00000000000..c8f4ce88f65 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c > @@ -0,0 +1,47 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vdiv-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D VAL * 3; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D 3); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D VAL * 5; \ > + vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D 5); > + > +#define RUN_ALL() \ > + RUN(int16_t, -1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, -3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, -5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c > new file mode 100644 > index 00000000000..9759401b9ef > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c > @@ -0,0 +1,9 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vdiv-template.h" > + > +/* TODO: Implement vector type promotion. We should have 6 vdiv.vv > here. */ > + > +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */ > +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c > new file mode 100644 > index 00000000000..40fdfbd8922 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c > @@ -0,0 +1,9 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vdiv-template.h" > + > +/* TODO: Implement vector type promotion. We should have 6 vdiv.vv > here. */ > + > +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */ > +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h > new file mode 100644 > index 00000000000..7fbba7b4133 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h > @@ -0,0 +1,34 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] / b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] / b; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) > + > +TEST_ALL() > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c > new file mode 100644 > index 00000000000..90e5c971150 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c > @@ -0,0 +1,47 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vmax-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D 0; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vmax_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D 0 > VAL ? 0 : VAL); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D 0; \ > + vmaxs_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D 0 > VAL ? 0 : VAL); > + > +#define RUN_ALL() \ > + RUN(int16_t, -1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, -3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, -5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c > new file mode 100644 > index 00000000000..46a321289fc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vmax-template.h" > + > +/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */ > +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c > new file mode 100644 > index 00000000000..03496305901 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vmax-template.h" > + > +/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */ > +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h > new file mode 100644 > index 00000000000..df0f9f2aeeb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h > @@ -0,0 +1,34 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] > b[i] ? a[i] : b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vmaxs_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] > b ? a[i] : b; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) > + > +TEST_ALL() > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c > new file mode 100644 > index 00000000000..34f9348498b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c > @@ -0,0 +1,47 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vmin-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D 0; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vmin_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D 0 < VAL ? 0 : VAL); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D 0; \ > + vmins_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D 0 < VAL ? 0 : VAL); > + > +#define RUN_ALL() \ > + RUN(int16_t, -1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, -3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, -5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c > new file mode 100644 > index 00000000000..da3bb179ba7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vmin-template.h" > + > +/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */ > +/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c > new file mode 100644 > index 00000000000..ff1d0bbf32e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vmin-template.h" > + > +/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */ > +/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h > new file mode 100644 > index 00000000000..459f58ddec1 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h > @@ -0,0 +1,34 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] < b[i] ? a[i] : b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vmins_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] < b ? a[i] : b; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) > + > +TEST_ALL() > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c > new file mode 100644 > index 00000000000..19e38ca8ff1 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c > @@ -0,0 +1,47 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vmul-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D 2; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D 2 * VAL); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D 3; \ > + vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D 3 * VAL); > + > +#define RUN_ALL() \ > + RUN(int16_t, -1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, -3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, -5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c > new file mode 100644 > index 00000000000..f4df04d15eb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c > @@ -0,0 +1,6 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vmul-template.h" > + > +/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c > new file mode 100644 > index 00000000000..a21bae4708f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c > @@ -0,0 +1,6 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vmul-template.h" > + > +/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h > new file mode 100644 > index 00000000000..b029c06efd6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h > @@ -0,0 +1,34 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] * b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] * b; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) > + > +TEST_ALL() > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c > new file mode 100644 > index 00000000000..e5eb1c48f73 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c > @@ -0,0 +1,69 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vor-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D 123; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vor_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D (123 | VAL)); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D 123; \ > + vors_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D (123 | VAL)); > + > +#define RUN3(TYPE,VAL) \ > + TYPE ai##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + ai##TYPE[i] =3D VAL; \ > + vori_##TYPE (ai##TYPE, ai##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (ai##TYPE[i] =3D=3D (VAL | 15)); > + > +#define RUN3M(TYPE,VAL) \ > + TYPE aim##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + aim##TYPE[i] =3D VAL; \ > + vorim_##TYPE (aim##TYPE, aim##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (aim##TYPE[i] =3D=3D (VAL | -16)); > + > +#define RUN_ALL() \ > + RUN(int16_t, -1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, -3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, -5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) \ > + RUN3M(int16_t, 13) \ > + RUN3(uint16_t, 14) \ > + RUN3M(int32_t, 15) \ > + RUN3(uint32_t, 16) \ > + RUN3M(int64_t, 17) \ > + RUN3(uint64_t, 18) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c > new file mode 100644 > index 00000000000..fc76d1c3b3e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vor-template.h" > + > +/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */ > +/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c > new file mode 100644 > index 00000000000..d364871fd4f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vor-template.h" > + > +/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */ > +/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h > new file mode 100644 > index 00000000000..859ae67c5ee > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h > @@ -0,0 +1,56 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] | b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vors_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] | b; \ > + } > + > +#define TEST3_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vori_##TYPE (TYPE *dst, TYPE *a, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] | 15; \ > + } > + > +#define TEST3M_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vorim_##TYPE (TYPE *dst, TYPE *a, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] | -16; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) \ > + TEST3M_TYPE(int16_t) \ > + TEST3_TYPE(uint16_t) \ > + TEST3M_TYPE(int32_t) \ > + TEST3_TYPE(uint32_t) \ > + TEST3M_TYPE(int64_t) \ > + TEST3_TYPE(uint64_t) > + > +TEST_ALL() > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c > new file mode 100644 > index 00000000000..db3bee3c49a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c > @@ -0,0 +1,47 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vrem-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D 37; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vrem_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D 37 % VAL); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D 89; \ > + vrems_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D 89 % VAL); > + > +#define RUN_ALL() \ > + RUN(int16_t, -1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, -3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, -5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c > new file mode 100644 > index 00000000000..28cba510a93 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c > @@ -0,0 +1,9 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vrem-template.h" > + > +/* TODO: Implement vector type promotion. We should have 6 vrem.vv > here. */ > + > +/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */ > +/* { dg-final { scan-assembler-times {\tvremu\.vv} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c > new file mode 100644 > index 00000000000..68dbdcf021a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c > @@ -0,0 +1,9 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vrem-template.h" > + > +/* TODO: Implement vector type promotion. We should have 6 vrem.vv > here. */ > + > +/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */ > +/* { dg-final { scan-assembler-times {\tvremu\.vv} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h > new file mode 100644 > index 00000000000..71eebc8b645 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h > @@ -0,0 +1,34 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vrem_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] % b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vrems_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] % b; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) > + > +TEST_ALL() > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run.c > new file mode 100644 > index 00000000000..8c6d8e88d1a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run.c > @@ -0,0 +1,47 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vsub-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D 999; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vsub_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D 999 - VAL); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D 999; \ > + vsubs_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D 999 - VAL); > + > +#define RUN_ALL() \ > + RUN(int16_t, 1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, 3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, 5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, 7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, 9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, 11) \ > + RUN2(uint64_t, 12) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c > new file mode 100644 > index 00000000000..e2bdd0fe904 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c > @@ -0,0 +1,6 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vsub-template.h" > + > +/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c > new file mode 100644 > index 00000000000..26867a0bbd7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c > @@ -0,0 +1,6 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vsub-template.h" > + > +/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h > new file mode 100644 > index 00000000000..0566f3dcbfb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h > @@ -0,0 +1,34 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vsub_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] - b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vsubs_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] - b; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) > + > +TEST_ALL() > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run-template.h > new file mode 100644 > index 00000000000..e69de29bb2d > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c > new file mode 100644 > index 00000000000..68b9648738f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c > @@ -0,0 +1,69 @@ > +/* { dg-do run { target { riscv_vector } } } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vxor-template.h" > + > +#include > + > +#define SZ 512 > + > +#define RUN(TYPE,VAL) \ > + TYPE a##TYPE[SZ]; \ > + TYPE b##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + { \ > + a##TYPE[i] =3D 123; \ > + b##TYPE[i] =3D VAL; \ > + } \ > + vxor_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (a##TYPE[i] =3D=3D (123 ^ VAL)); > + > +#define RUN2(TYPE,VAL) \ > + TYPE as##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + as##TYPE[i] =3D 123; \ > + vxors_##TYPE (as##TYPE, as##TYPE, VAL, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (as##TYPE[i] =3D=3D (123 ^ VAL)); > + > +#define RUN3(TYPE,VAL) \ > + TYPE ai##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + ai##TYPE[i] =3D VAL; \ > + vxori_##TYPE (ai##TYPE, ai##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (ai##TYPE[i] =3D=3D (VAL ^ 15)); > + > +#define RUN3M(TYPE,VAL) \ > + TYPE aim##TYPE[SZ]; \ > + for (int i =3D 0; i < SZ; i++) \ > + aim##TYPE[i] =3D VAL; \ > + vxorim_##TYPE (aim##TYPE, aim##TYPE, SZ); \ > + for (int i =3D 0; i < SZ; i++) \ > + assert (aim##TYPE[i] =3D=3D (VAL ^ -16)); > + > +#define RUN_ALL() \ > + RUN(int16_t, -1) \ > + RUN(uint16_t, 2) \ > + RUN(int32_t, -3) \ > + RUN(uint32_t, 4) \ > + RUN(int64_t, -5) \ > + RUN(uint64_t, 6) \ > + RUN2(int16_t, -7) \ > + RUN2(uint16_t, 8) \ > + RUN2(int32_t, -9) \ > + RUN2(uint32_t, 10) \ > + RUN2(int64_t, -11) \ > + RUN2(uint64_t, 12) \ > + RUN3M(int16_t, 13) \ > + RUN3(uint16_t, 14) \ > + RUN3M(int32_t, 15) \ > + RUN3(uint32_t, 16) \ > + RUN3M(int64_t, 17) \ > + RUN3(uint64_t, 18) > + > +int main () > +{ > + RUN_ALL() > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c > new file mode 100644 > index 00000000000..fbef4a45770 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv3= 2gcv > -mabi=3Dilp32d --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vxor-template.h" > + > +/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */ > +/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c > new file mode 100644 > index 00000000000..3e5885eb659 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-std=3Dc99 -fno-vect-cost-model -march=3Drv6= 4gcv > --param=3Driscv-autovec-preference=3Dfixed-vlmax" } */ > + > +#include "vxor-template.h" > + > +/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */ > +/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h > new file mode 100644 > index 00000000000..954a247f539 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h > @@ -0,0 +1,56 @@ > +#include > + > +#define TEST_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] ^ b[i]; \ > + } > + > +#define TEST2_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vxors_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] ^ b; \ > + } > + > +#define TEST3_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vxori_##TYPE (TYPE *dst, TYPE *a, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] ^ 15; \ > + } > + > +#define TEST3M_TYPE(TYPE) \ > + __attribute__((noipa)) \ > + void vxorim_##TYPE (TYPE *dst, TYPE *a, int n) \ > + { \ > + for (int i =3D 0; i < n; i++) \ > + dst[i] =3D a[i] ^ -16; \ > + } > + > +/* *int8_t not autovec currently. */ > +#define TEST_ALL() \ > + TEST_TYPE(int16_t) \ > + TEST_TYPE(uint16_t) \ > + TEST_TYPE(int32_t) \ > + TEST_TYPE(uint32_t) \ > + TEST_TYPE(int64_t) \ > + TEST_TYPE(uint64_t) \ > + TEST2_TYPE(int16_t) \ > + TEST2_TYPE(uint16_t) \ > + TEST2_TYPE(int32_t) \ > + TEST2_TYPE(uint32_t) \ > + TEST2_TYPE(int64_t) \ > + TEST2_TYPE(uint64_t) \ > + TEST3M_TYPE(int16_t) \ > + TEST3_TYPE(uint16_t) \ > + TEST3M_TYPE(int32_t) \ > + TEST3_TYPE(uint32_t) \ > + TEST3M_TYPE(int64_t) \ > + TEST3_TYPE(uint64_t) > + > +TEST_ALL() > -- > 2.40.0 > > > > --00000000000027641105fb69059f--