From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id 8492B382DE20 for ; Thu, 27 Oct 2022 03:12:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8492B382DE20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62f.google.com with SMTP id d26so879522eje.10 for ; Wed, 26 Oct 2022 20:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=7nL+eEjihJDcNv4H2wPNgBjigb/X4bRKBHgbUhj4yko=; b=MmM2ldPuyr/kfeg9E68Qzj2C4elxsZUERt2XdJMDHJs/bIQVIsh5WLQxHQ1Q84fdfG ihFU8lX6HzV4t+0b2m3k30raDEwQxZU9f5aNW1Vm1pDvGhrExJUfo4r2dy+mSgPOCWiL Qjhw90TOZLfcgLWt5rdWuMPnJDRWv0Wb7orOEMhxTbj+uXsqjAtPH4yemcmcByUVxMZq 4GBEmt5zd5+miqShYWBf2ntVzZAfb1neL/PSfHOXpnjpBekGWJQfTgCBQHqa61RiyQLW iB5RSjvfvE+2RuLOuxAUH8PRXfaZIbb52dTSmPxMJyD80QgXaIwQQ2Ilh5LNjnZWJy41 EkYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7nL+eEjihJDcNv4H2wPNgBjigb/X4bRKBHgbUhj4yko=; b=67IEGR13qDx1BVcIcq2Bk/q/F/nPYAcmaTmbF9PQ4Q1TQ7sp8sFWdPqSgVODbtsOPs qUT87rnDkQuQ0TWItnZt7Qclw7o6JfKrnqI7qz9LUuG5v0pKWBQ6rTjBS/oszwa/XJ6D qLn2NEcF22CHN6Qv2DMzAxl8vrEQUCNEiVnHdLrgDHPHfXPB3GnrCXlLjM6tl7tYzqeM /VcJfnzQnWJaoEr8n4GPlBkhKklZMgPYQ250up8f/CcA99vW7khXNBJbj//lrTmwJpTt xTwLw/xK+HLlfMPqUmUJMI0HR9QWaQUcyt1TClc2DmrrMi1NXUqQwKlLocF+fWEVk5qT qrbg== X-Gm-Message-State: ACrzQf1CrFxdftiQdKnjo2cGKppEefK4DWEZtA/vRLbGeXNWjkFIpyUb EeRPa5FrJqd9lYECu27voWv4V/KtpzdCslaeF4o= X-Google-Smtp-Source: AMsMyM72Sf+nbCLE+Uy/rgVfDS8ceYGTWfQuaBaDD7Z+w5M7/H1X7WFidLMdQdhOevckmNoUrD31KRRanhxss/XeKFs= X-Received: by 2002:a17:906:fe45:b0:788:15a5:7495 with SMTP id wz5-20020a170906fe4500b0078815a57495mr40784445ejb.633.1666840338311; Wed, 26 Oct 2022 20:12:18 -0700 (PDT) MIME-Version: 1.0 References: <20221020093235.5071-1-jiawei@iscas.ac.cn> <20221020093235.5071-4-jiawei@iscas.ac.cn> In-Reply-To: <20221020093235.5071-4-jiawei@iscas.ac.cn> From: Kito Cheng Date: Thu, 27 Oct 2022 11:12:06 +0800 Message-ID: Subject: Re: [v4 PATCH 3/4] RISC-V: Limit regs use for z*inx extension. To: jiawei Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, wuwei2016@iscas.ac.cn Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hmmm 2 issue, but I fixed that anyway, otherwise LGTM. > From: Jiawei > > Limit z*inx abi support with 'ilp32','ilp32e','lp64' only. > Use GPR instead FPR when 'zfinx' enable, Only use even registers > in RV32 when 'zdinx' enable. > Enable FLOAT16 when Zhinx/Zhinxmin enabled. > > Co-Authored-By: Sinan Lin. > > gcc/ChangeLog: > > * config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS > use while Zfinx is enable. > * config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd > registers use when Zdinx enable in RV32 cases. > (riscv_option_override): New target enable MASK_FDIV. > (riscv_libgcc_floating_mode_supported_p): New error info when > use incompatible arch&abi. > (riscv_excess_precision): New target enable FLOAT16. > > --- > gcc/config/riscv/constraints.md | 5 +++-- > gcc/config/riscv/riscv.cc | 21 +++++++++++++++++---- > 2 files changed, 20 insertions(+), 6 deletions(-) > > diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md > index 8997284f32e..c53e0f38920 100644 > --- a/gcc/config/riscv/constraints.md > +++ b/gcc/config/riscv/constraints.md > @@ -21,8 +21,9 @@ > > ;; Register constraints > > -(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" > - "A floating-point register (if available).") > +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : > + (TARGET_ZFINX ? GR_REGS) : NO_REGS" (TARGET_ZFINX ? GR_REGS : NO_REGS)" > + "A floating-point register (if available, reuse GPR as FPR when use zfinx).") > > (define_register_constraint "j" "SIBCALL_REGS" > "@internal") > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index ad57b995e7b..38631605b2c 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5356,6 +5356,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) > != call_used_or_fixed_reg_p (regno + i)) > return false; > > + /* Only use even registers in RV32 ZDINX */ > + if (!TARGET_64BIT && TARGET_ZDINX){ > + if (GET_MODE_CLASS (mode) == MODE_FLOAT && > + GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode)) > + return !(regno & 1); > + } > + > return true; > } > > @@ -5595,7 +5602,7 @@ riscv_option_override (void) > error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); > > /* Likewise floating-point division and square root. */ > - if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) > + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0) > target_flags |= MASK_FDIV; > > /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune > @@ -5641,6 +5648,11 @@ riscv_option_override (void) > if (TARGET_RVE && riscv_abi != ABI_ILP32E) > error ("rv32e requires ilp32e ABI"); > > + // Zfinx require abi ilp32,ilp32e or lp64. > + if (TARGET_ZFINX && riscv_abi != ABI_ILP32 > + && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) > + error ("z*inx requires ABI ilp32, ilp32e or lp64"); > + > /* We do not yet support ILP32 on RV64. */ > if (BITS_PER_WORD != POINTER_SIZE) > error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); > @@ -6273,7 +6285,7 @@ riscv_libgcc_floating_mode_supported_p (scalar_float_mode mode) > precision of the _FloatN type; evaluate all other operations and > constants to the range and precision of the semantic type; > > - If we have the zfh extensions then we support _Float16 in native > + If we have the zfh/zhinx extensions then we support _Float16 in native > precision, so we should set this to 16. */ > static enum flt_eval_method > riscv_excess_precision (enum excess_precision_type type) > @@ -6282,8 +6294,9 @@ riscv_excess_precision (enum excess_precision_type type) > { > case EXCESS_PRECISION_TYPE_FAST: > case EXCESS_PRECISION_TYPE_STANDARD: > - return (TARGET_ZFH ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 > - : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT); > + return ((TARGET_ZFH || TARGET_ZHINX || TARGET_ZHINXMIN) Should be (TARGET_ZFH || TARGET_ZHINX) > + ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 > + : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT); > case EXCESS_PRECISION_TYPE_IMPLICIT: > case EXCESS_PRECISION_TYPE_FLOAT16: > return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16; > -- > 2.25.1 >