From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe35.google.com (mail-vs1-xe35.google.com [IPv6:2607:f8b0:4864:20::e35]) by sourceware.org (Postfix) with ESMTPS id 498C5385800A for ; Mon, 19 Dec 2022 15:09:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 498C5385800A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe35.google.com with SMTP id k185so8996674vsc.2 for ; Mon, 19 Dec 2022 07:09:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=M5NDMTTAxyGnk+AlXQekIxfrvt3+JO0bxNkBg9UWUH0=; b=LXZ54mOLpJ5HeMm1isfyugesf4pMRAsbjuCC/kyYghU0qnI4vEe4/qQyiQH9NFOXtJ 4t4j2V/DiFPpqliYK3Zy6SOr9U3H8iS4jMUQ3R5ppGS7OpFf65skOaWFJi3E5Z7hCFMC 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AA0mqf40GoMCnygy6QU1vXkmwpXWyByR8AG4hLwHfmnsZ3kzC0ZN3MipGtaAeU2WOUFnF7iwNpvpb3Oslc0R8BAZ5hs= X-Received: by 2002:a67:fb52:0:b0:3b1:1914:e63d with SMTP id e18-20020a67fb52000000b003b11914e63dmr15478859vsr.40.1671462548061; Mon, 19 Dec 2022 07:09:08 -0800 (PST) MIME-Version: 1.0 References: <20221214081548.253313-1-juzhe.zhong@rivai.ai> In-Reply-To: <20221214081548.253313-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Mon, 19 Dec 2022 23:08:54 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add testcases for VSETVL PASS 3 To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: GCC Patches , Palmer Dabbelt Content-Type: multipart/alternative; boundary="0000000000006ec5ef05f02fb323" X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000006ec5ef05f02fb323 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Commited to trunk =E6=96=BC 2022=E5=B9=B412=E6=9C=8814=E6=97=A5 =E9=80= =B1=E4=B8=89 16:16 =E5=AF=AB=E9=81=93=EF=BC=9A > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: New test. > > --- > .../riscv/rvv/vsetvl/vlmax_miss_default-1.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-10.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-11.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-12.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-13.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-14.c | 189 ++++++++++++++ > .../riscv/rvv/vsetvl/vlmax_miss_default-15.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-16.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-17.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-18.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-19.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-2.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-20.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-21.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-22.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-23.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-24.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-25.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-26.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-27.c | 38 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-28.c | 231 ++++++++++++++++++ > .../riscv/rvv/vsetvl/vlmax_miss_default-3.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-4.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-5.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-6.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-7.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-8.c | 32 +++ > .../riscv/rvv/vsetvl/vlmax_miss_default-9.c | 32 +++ > 28 files changed, 1330 insertions(+) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c > > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c > new file mode 100644 > index 00000000000..d801428004e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 100); > + *(vint8mf8_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 200); > + *(vint8mf8_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 300); > + *(vint8mf8_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + i); > + *(vint8mf8_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c > new file mode 100644 > index 00000000000..d96e9b2d7ab > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vuint16mf2_t v =3D *(vuint16mf2_t*)(in + 100); > + *(vuint16mf2_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vuint16mf2_t v =3D *(vuint16mf2_t*)(in + 200); > + *(vuint16mf2_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vuint16mf2_t v =3D *(vuint16mf2_t*)(in + 300); > + *(vuint16mf2_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint16mf2_t v =3D *(vuint16mf2_t*)(in + i); > + *(vuint16mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c > new file mode 100644 > index 00000000000..de967f78bc6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 100); > + *(vint32mf2_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 300); > + *(vint32mf2_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + i); > + *(vint32mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c > new file mode 100644 > index 00000000000..8342edb353a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vuint32mf2_t v =3D *(vuint32mf2_t*)(in + 100); > + *(vuint32mf2_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vuint32mf2_t v =3D *(vuint32mf2_t*)(in + 200); > + *(vuint32mf2_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vuint32mf2_t v =3D *(vuint32mf2_t*)(in + 300); > + *(vuint32mf2_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint32mf2_t v =3D *(vuint32mf2_t*)(in + i); > + *(vuint32mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c > new file mode 100644 > index 00000000000..82cd0d36913 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 100); > + *(vfloat32mf2_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 200); > + *(vfloat32mf2_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 300); > + *(vfloat32mf2_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + i); > + *(vfloat32mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c > new file mode 100644 > index 00000000000..5e08b23178b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c > @@ -0,0 +1,189 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vbool64_t v =3D *(vbool64_t*)(in + 100); > + *(vbool64_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vbool64_t v =3D *(vbool64_t*)(in + 200); > + *(vbool64_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vbool64_t v =3D *(vbool64_t*)(in + 300); > + *(vbool64_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool64_t v =3D *(vbool64_t*)(in + i); > + *(vbool64_t*)(out + i) =3D v; > + } > +} > + > +void f2 (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vbool32_t v =3D *(vbool32_t*)(in + 100); > + *(vbool32_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vbool32_t v =3D *(vbool32_t*)(in + 200); > + *(vbool32_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vbool32_t v =3D *(vbool32_t*)(in + 300); > + *(vbool32_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool32_t v =3D *(vbool32_t*)(in + i); > + *(vbool32_t*)(out + i) =3D v; > + } > +} > + > +void f3 (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vbool16_t v =3D *(vbool16_t*)(in + 100); > + *(vbool16_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vbool16_t v =3D *(vbool16_t*)(in + 200); > + *(vbool16_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vbool16_t v =3D *(vbool16_t*)(in + 300); > + *(vbool16_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool16_t v =3D *(vbool16_t*)(in + i); > + *(vbool16_t*)(out + i) =3D v; > + } > +} > + > +void f4 (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vbool8_t v =3D *(vbool8_t*)(in + 100); > + *(vbool8_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vbool8_t v =3D *(vbool8_t*)(in + 200); > + *(vbool8_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vbool8_t v =3D *(vbool8_t*)(in + 300); > + *(vbool8_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool8_t v =3D *(vbool8_t*)(in + i); > + *(vbool8_t*)(out + i) =3D v; > + } > +} > + > +void f5 (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vbool4_t v =3D *(vbool4_t*)(in + 100); > + *(vbool4_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vbool4_t v =3D *(vbool4_t*)(in + 200); > + *(vbool4_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vbool4_t v =3D *(vbool4_t*)(in + 300); > + *(vbool4_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool4_t v =3D *(vbool4_t*)(in + i); > + *(vbool4_t*)(out + i) =3D v; > + } > +} > + > +void f6 (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vbool2_t v =3D *(vbool2_t*)(in + 100); > + *(vbool2_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vbool2_t v =3D *(vbool2_t*)(in + 200); > + *(vbool2_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vbool2_t v =3D *(vbool2_t*)(in + 300); > + *(vbool2_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool2_t v =3D *(vbool2_t*)(in + i); > + *(vbool2_t*)(out + i) =3D v; > + } > +} > + > +void f7 (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vbool1_t v =3D *(vbool1_t*)(in + 100); > + *(vbool1_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vbool1_t v =3D *(vbool1_t*)(in + 200); > + *(vbool1_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vbool1_t v =3D *(vbool1_t*)(in + 300); > + *(vbool1_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool1_t v =3D *(vbool1_t*)(in + i); > + *(vbool1_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 1,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 8,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c > new file mode 100644 > index 00000000000..267d1bd5cf6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 100); > + *(vint8mf8_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 200); > + *(vint8mf8_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vint8mf8_t v =3D *(vint8mf8_t*)(in + 300); > + *(vint8mf8_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vint8mf8_t v =3D *(vint8mf8_t*)(in + i); > + *(vint8mf8_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c > new file mode 100644 > index 00000000000..3e6c51ad9af > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + 100); > + *(vuint8mf8_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + 200); > + *(vuint8mf8_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + 300); > + *(vuint8mf8_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + i); > + *(vuint8mf8_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c > new file mode 100644 > index 00000000000..ae2caedff27 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vint8mf4_t v =3D *(vint8mf4_t*)(in + 100); > + *(vint8mf4_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vint8mf4_t v =3D *(vint8mf4_t*)(in + 200); > + *(vint8mf4_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vint8mf4_t v =3D *(vint8mf4_t*)(in + 300); > + *(vint8mf4_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vint8mf4_t v =3D *(vint8mf4_t*)(in + i); > + *(vint8mf4_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c > new file mode 100644 > index 00000000000..2378b4006c0 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vuint8mf4_t v =3D *(vuint8mf4_t*)(in + 100); > + *(vuint8mf4_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vuint8mf4_t v =3D *(vuint8mf4_t*)(in + 200); > + *(vuint8mf4_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vuint8mf4_t v =3D *(vuint8mf4_t*)(in + 300); > + *(vuint8mf4_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint8mf4_t v =3D *(vuint8mf4_t*)(in + i); > + *(vuint8mf4_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c > new file mode 100644 > index 00000000000..1de8fc461dc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vint8mf2_t v =3D *(vint8mf2_t*)(in + 100); > + *(vint8mf2_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vint8mf2_t v =3D *(vint8mf2_t*)(in + 200); > + *(vint8mf2_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vint8mf2_t v =3D *(vint8mf2_t*)(in + 300); > + *(vint8mf2_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vint8mf2_t v =3D *(vint8mf2_t*)(in + i); > + *(vint8mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c > new file mode 100644 > index 00000000000..6c77a94ae63 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + 100); > + *(vuint8mf8_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + 200); > + *(vuint8mf8_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + 300); > + *(vuint8mf8_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint8mf8_t v =3D *(vuint8mf8_t*)(in + i); > + *(vuint8mf8_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c > new file mode 100644 > index 00000000000..41100cb04a3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vuint8mf2_t v =3D *(vuint8mf2_t*)(in + 100); > + *(vuint8mf2_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vuint8mf2_t v =3D *(vuint8mf2_t*)(in + 200); > + *(vuint8mf2_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vuint8mf2_t v =3D *(vuint8mf2_t*)(in + 300); > + *(vuint8mf2_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint8mf2_t v =3D *(vuint8mf2_t*)(in + i); > + *(vuint8mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c > new file mode 100644 > index 00000000000..070899e6e49 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vint16mf4_t v =3D *(vint16mf4_t*)(in + 100); > + *(vint16mf4_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vint16mf4_t v =3D *(vint16mf4_t*)(in + 200); > + *(vint16mf4_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vint16mf4_t v =3D *(vint16mf4_t*)(in + 300); > + *(vint16mf4_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vint16mf4_t v =3D *(vint16mf4_t*)(in + i); > + *(vint16mf4_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c > new file mode 100644 > index 00000000000..1e96191a9fc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vuint16mf4_t v =3D *(vuint16mf4_t*)(in + 100); > + *(vuint16mf4_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vuint16mf4_t v =3D *(vuint16mf4_t*)(in + 200); > + *(vuint16mf4_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vuint16mf4_t v =3D *(vuint16mf4_t*)(in + 300); > + *(vuint16mf4_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint16mf4_t v =3D *(vuint16mf4_t*)(in + i); > + *(vuint16mf4_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c > new file mode 100644 > index 00000000000..fa6420822f2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vint16mf2_t v =3D *(vint16mf2_t*)(in + 100); > + *(vint16mf2_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vint16mf2_t v =3D *(vint16mf2_t*)(in + 200); > + *(vint16mf2_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vint16mf2_t v =3D *(vint16mf2_t*)(in + 300); > + *(vint16mf2_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vint16mf2_t v =3D *(vint16mf2_t*)(in + i); > + *(vint16mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c > new file mode 100644 > index 00000000000..d0352fccacf > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vuint16mf2_t v =3D *(vuint16mf2_t*)(in + 100); > + *(vuint16mf2_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vuint16mf2_t v =3D *(vuint16mf2_t*)(in + 200); > + *(vuint16mf2_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vuint16mf2_t v =3D *(vuint16mf2_t*)(in + 300); > + *(vuint16mf2_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint16mf2_t v =3D *(vuint16mf2_t*)(in + i); > + *(vuint16mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c > new file mode 100644 > index 00000000000..ad76c24d294 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 100); > + *(vint32mf2_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 200); > + *(vint32mf2_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vint32mf2_t v =3D *(vint32mf2_t*)(in + 300); > + *(vint32mf2_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vint32mf2_t v =3D *(vint32mf2_t*)(in + i); > + *(vint32mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c > new file mode 100644 > index 00000000000..71a3f4a06f6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vuint32mf2_t v =3D *(vuint32mf2_t*)(in + 100); > + *(vuint32mf2_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vuint32mf2_t v =3D *(vuint32mf2_t*)(in + 200); > + *(vuint32mf2_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vuint32mf2_t v =3D *(vuint32mf2_t*)(in + 300); > + *(vuint32mf2_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint32mf2_t v =3D *(vuint32mf2_t*)(in + i); > + *(vuint32mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c > new file mode 100644 > index 00000000000..613a028089b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c > @@ -0,0 +1,38 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 100); > + *(vfloat32mf2_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 200); > + *(vfloat32mf2_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + 300); > + *(vfloat32mf2_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vfloat32mf2_t v =3D *(vfloat32mf2_t*)(in + i); > + *(vfloat32mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c > new file mode 100644 > index 00000000000..6a2011b0290 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c > @@ -0,0 +1,231 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vbool64_t v =3D *(vbool64_t*)(in + 100); > + *(vbool64_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vbool64_t v =3D *(vbool64_t*)(in + 200); > + *(vbool64_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vbool64_t v =3D *(vbool64_t*)(in + 300); > + *(vbool64_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool64_t v =3D *(vbool64_t*)(in + i); > + *(vbool64_t*)(out + i) =3D v; > + } > +} > + > +void f2 (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vbool32_t v =3D *(vbool32_t*)(in + 100); > + *(vbool32_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vbool32_t v =3D *(vbool32_t*)(in + 200); > + *(vbool32_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vbool32_t v =3D *(vbool32_t*)(in + 300); > + *(vbool32_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool32_t v =3D *(vbool32_t*)(in + i); > + *(vbool32_t*)(out + i) =3D v; > + } > +} > + > +void f3 (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vbool16_t v =3D *(vbool16_t*)(in + 100); > + *(vbool16_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vbool16_t v =3D *(vbool16_t*)(in + 200); > + *(vbool16_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vbool16_t v =3D *(vbool16_t*)(in + 300); > + *(vbool16_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool16_t v =3D *(vbool16_t*)(in + i); > + *(vbool16_t*)(out + i) =3D v; > + } > +} > + > +void f4 (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vbool8_t v =3D *(vbool8_t*)(in + 100); > + *(vbool8_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vbool8_t v =3D *(vbool8_t*)(in + 200); > + *(vbool8_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vbool8_t v =3D *(vbool8_t*)(in + 300); > + *(vbool8_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool8_t v =3D *(vbool8_t*)(in + i); > + *(vbool8_t*)(out + i) =3D v; > + } > +} > + > +void f5 (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vbool4_t v =3D *(vbool4_t*)(in + 100); > + *(vbool4_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vbool4_t v =3D *(vbool4_t*)(in + 200); > + *(vbool4_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vbool4_t v =3D *(vbool4_t*)(in + 300); > + *(vbool4_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool4_t v =3D *(vbool4_t*)(in + i); > + *(vbool4_t*)(out + i) =3D v; > + } > +} > + > +void f6 (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vbool2_t v =3D *(vbool2_t*)(in + 100); > + *(vbool2_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vbool2_t v =3D *(vbool2_t*)(in + 200); > + *(vbool2_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vbool2_t v =3D *(vbool2_t*)(in + 300); > + *(vbool2_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool2_t v =3D *(vbool2_t*)(in + i); > + *(vbool2_t*)(out + i) =3D v; > + } > +} > + > +void f7 (void * restrict in, void * restrict out, int n, int cond) > +{ > + switch (cond) > + { > + case 1:{ > + vbool1_t v =3D *(vbool1_t*)(in + 100); > + *(vbool1_t*)(out + 100) =3D v; > + break; > + } > + case 2:{ > + vbool1_t v =3D *(vbool1_t*)(in + 200); > + *(vbool1_t*)(out + 100) =3D v; > + break; > + } > + case 3:{ > + vbool1_t v =3D *(vbool1_t*)(in + 300); > + *(vbool1_t*)(out + 100) =3D v; > + break; > + } > + default:{ > + break; > + } > + } > + for (int i =3D 0; i < n; i++) > + { > + vbool1_t v =3D *(vbool1_t*)(in + i); > + *(vbool1_t*)(out + i) =3D v; > + } > +} > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 1,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 8,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= 8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > + > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c > new file mode 100644 > index 00000000000..a03f36ab1c5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vint8mf4_t v =3D *(vint8mf4_t*)(in + 100); > + *(vint8mf4_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vint8mf4_t v =3D *(vint8mf4_t*)(in + 200); > + *(vint8mf4_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vint8mf4_t v =3D *(vint8mf4_t*)(in + 300); > + *(vint8mf4_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vint8mf4_t v =3D *(vint8mf4_t*)(in + i); > + *(vint8mf4_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c > new file mode 100644 > index 00000000000..ab16ef2e148 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vuint8mf4_t v =3D *(vuint8mf4_t*)(in + 100); > + *(vuint8mf4_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vuint8mf4_t v =3D *(vuint8mf4_t*)(in + 200); > + *(vuint8mf4_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vuint8mf4_t v =3D *(vuint8mf4_t*)(in + 300); > + *(vuint8mf4_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint8mf4_t v =3D *(vuint8mf4_t*)(in + i); > + *(vuint8mf4_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c > new file mode 100644 > index 00000000000..7722b9eef1f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vint8mf2_t v =3D *(vint8mf2_t*)(in + 100); > + *(vint8mf2_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vint8mf2_t v =3D *(vint8mf2_t*)(in + 200); > + *(vint8mf2_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vint8mf2_t v =3D *(vint8mf2_t*)(in + 300); > + *(vint8mf2_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vint8mf2_t v =3D *(vint8mf2_t*)(in + i); > + *(vint8mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c > new file mode 100644 > index 00000000000..7ec497129b1 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vuint8mf2_t v =3D *(vuint8mf2_t*)(in + 100); > + *(vuint8mf2_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vuint8mf2_t v =3D *(vuint8mf2_t*)(in + 200); > + *(vuint8mf2_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vuint8mf2_t v =3D *(vuint8mf2_t*)(in + 300); > + *(vuint8mf2_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint8mf2_t v =3D *(vuint8mf2_t*)(in + i); > + *(vuint8mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m= f2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c > new file mode 100644 > index 00000000000..2772de06151 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vint16mf4_t v =3D *(vint16mf4_t*)(in + 100); > + *(vint16mf4_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vint16mf4_t v =3D *(vint16mf4_t*)(in + 200); > + *(vint16mf4_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vint16mf4_t v =3D *(vint16mf4_t*)(in + 300); > + *(vint16mf4_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vint16mf4_t v =3D *(vint16mf4_t*)(in + i); > + *(vint16mf4_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c > new file mode 100644 > index 00000000000..124c09b485a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vuint16mf4_t v =3D *(vuint16mf4_t*)(in + 100); > + *(vuint16mf4_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vuint16mf4_t v =3D *(vuint16mf4_t*)(in + 200); > + *(vuint16mf4_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vuint16mf4_t v =3D *(vuint16mf4_t*)(in + 300); > + *(vuint16mf4_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vuint16mf4_t v =3D *(vuint16mf4_t*)(in + i); > + *(vuint16mf4_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf4,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts > "-g" } } } } */ > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c > b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c > new file mode 100644 > index 00000000000..7699a4408ad > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32" } */ > + > +#include "riscv_vector.h" > + > +/* The for loop body should not have vsetvl instruction. */ > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + if (cond =3D=3D 1) > + { > + vint16mf2_t v =3D *(vint16mf2_t*)(in + 100); > + *(vint16mf2_t*)(out + 100) =3D v; > + } > + else if (cond =3D=3D 2) > + { > + vint16mf2_t v =3D *(vint16mf2_t*)(in + 200); > + *(vint16mf2_t*)(out + 200) =3D v; > + } > + else if (cond =3D=3D 3) > + { > + vint16mf2_t v =3D *(vint16mf2_t*)(in + 300); > + *(vint16mf2_t*)(out + 300) =3D v; > + } > + for (int i =3D 0; i < n; i++) > + { > + vint16mf2_t v =3D *(vint16mf2_t*)(in + i); > + *(vint16mf2_t*)(out + i) =3D v; > + } > +} > + > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf2,\s*t[au],\s*m[au]} > 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-op= ts > "-g" } } } } */ > +/* { dg-final { scan-assembler-times > {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*= mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} > 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" > no-opts "-g" } } } } */ > -- > 2.36.3 > > --0000000000006ec5ef05f02fb323--