From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x935.google.com (mail-ua1-x935.google.com [IPv6:2607:f8b0:4864:20::935]) by sourceware.org (Postfix) with ESMTPS id C101B3858C54 for ; Fri, 12 May 2023 01:32:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C101B3858C54 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x935.google.com with SMTP id a1e0cc1a2514c-77d50a1c8deso2815529241.3 for ; Thu, 11 May 2023 18:32:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683855171; x=1686447171; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=qvKbTclTpdB3fu+lJC+ry7dPS/NomrkjR08aPkZHHko=; b=c7rm2K6svSOt+JXHXFCvB6nBJQjYmacoGdc7VA7yPAOuaBHrmnw0LyLajmRQY9I7yR P3fFF1uwRfjZouiVg9E8oUYVjlyR7yi/PEsighxWh63ZDoI/hmlLQ3okGY6UbLx2iTai riuQ1cWBpGO07acgqZ9UuIoVXEdppBOTBV4zNCGGKcLqaQFe4ZAYjDicz5yDTMKrxTca oLvV1M5NCx6v+XvCRDxpslLwQ+w6EJItQ3w0009dE6nYzFFvz79O0vChJ8I6C7/ODsoO 7UqcOdTpf0mqcQxUx8eAexIKRtU9oPxuqUNXY2zMyo0txPNBBCeajZ+epnl+ulYS849G rJbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683855171; x=1686447171; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qvKbTclTpdB3fu+lJC+ry7dPS/NomrkjR08aPkZHHko=; b=JJyFXfSra/nFei+7LO0ieFxKhn0PBe+L1YEAsR0B9mWpjPEfPPYVITQ6VsK9Fu13hK wbnULaceyaSrt51PsbttWuO/HTcPeL3W1QhqbQya4PVxNC1u4HOzB6XMoAxpXfha7Fhq ovslw6xjLBueum+kSa5sYPxTkxOkq/Shl1PkWcMCYNvOLAIBOW4wPx1el94Rn6pbQ8hT AXtpry+VssHiqxFp4lLR602MS2p8KgQcdicoUtYTODq9Z4/AkeH9A+BEuvFSQo6QRzSY LtQKX6LGT2/kyhxq23WSx14pDz1UFSQHCFlfD2UaZUJuUqvfNsSo3yFbJiHqBPUWSA/l 4LcA== X-Gm-Message-State: AC+VfDzoKSsHqEg5fIKnDzJfPigpFBGKFl1y7mK8eq/4z0eTEvI+sxAB F14VtHxhfv+HoJ2PdLaSHCdJhA2I9YQeJBxCjBQ= X-Google-Smtp-Source: ACHHUZ7/az99YhhsxUzmJjLB25w85r0w4Rzzc56jyCul3nx5/RBAd5Luyh5B6Hvl4ZS43K0bfIJppBEm6rPqzlc3hG0= X-Received: by 2002:a1f:5f4e:0:b0:451:445b:6254 with SMTP id t75-20020a1f5f4e000000b00451445b6254mr5673914vkb.15.1683855170750; Thu, 11 May 2023 18:32:50 -0700 (PDT) MIME-Version: 1.0 References: <20230511222848.15044-1-palmer@rivosinc.com> In-Reply-To: <20230511222848.15044-1-palmer@rivosinc.com> From: Kito Cheng Date: Fri, 12 May 2023 09:32:37 +0800 Message-ID: Subject: Re: [PATCH v2] RISC-V: Add vector_scalar_shift_operand To: Palmer Dabbelt Cc: GCC Patches , =?UTF-8?B?6ZKf5bGF5ZOy?= Content-Type: multipart/alternative; boundary="0000000000004e4dde05fb751569" X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000004e4dde05fb751569 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LGTM, thanks :) Palmer Dabbelt =E6=96=BC 2023=E5=B9=B45=E6=9C=8812=E6= =97=A5 =E9=80=B1=E4=BA=94 06:32 =E5=AF=AB=E9=81=93=EF=BC=9A > The vector shift immediates happen to have the same constraints as some > of the CSR-related operands, but it's a different usage. This adds a > name for them, so I don't get confused again next time. > > gcc/ChangeLog: > > * config/riscv/autovec.md (shifts): Use > vector_scalar_shift_operand. > * config/riscv/predicates.md (vector_scalar_shift_operand): New > predicate. > --- > Still haven't built-tested it, my box is busy. > > Changes since v1 <20230511182555.26183-1-palmer@rivosinc.com>: > * Change the name to "vector_scalar_shift_operand", as per Juzhe's > suggestion. > * Add a missing second ";" in the comment. > --- > gcc/config/riscv/autovec.md | 2 +- > gcc/config/riscv/predicates.md | 5 +++++ > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index ac0c939d277..4561fcbe957 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -132,7 +132,7 @@ (define_expand "3" > [(set (match_operand:VI 0 "register_operand") > (any_shift:VI > (match_operand:VI 1 "register_operand") > - (match_operand: 2 "csr_operand")))] > + (match_operand: 2 "vector_scalar_shift_operand")))] > "TARGET_VECTOR" > { > if (!CONST_SCALAR_INT_P (operands[2])) > diff --git a/gcc/config/riscv/predicates.md > b/gcc/config/riscv/predicates.md > index e5adf06fa25..90e6f942c97 100644 > --- a/gcc/config/riscv/predicates.md > +++ b/gcc/config/riscv/predicates.md > @@ -43,6 +43,11 @@ (define_predicate "csr_operand" > (ior (match_operand 0 "const_csr_operand") > (match_operand 0 "register_operand"))) > > +;; V has 32-bit unsigned immediates. This happens to be the same > constraint as > +;; the csr_operand, but it's not CSR related. > +(define_predicate "vector_scalar_shift_operand" > + (match_operand 0 "csr_operand")) > + > (define_predicate "sle_operand" > (and (match_code "const_int") > (match_test "SMALL_OPERAND (INTVAL (op) + 1)"))) > -- > 2.40.0 > > --0000000000004e4dde05fb751569--