From: Kito Cheng <kito.cheng@gmail.com>
To: "Patrick O'Neill" <patrick@rivosinc.com>
Cc: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com,
palmer@dabbelt.com, gnu-toolchain@rivosinc.com,
Edwin Lu <ewlu@rivosinc.com>
Subject: Re: [PATCH v2 1/3] RISC-V: Add basic Zaamo and Zalrsc support
Date: Tue, 4 Jun 2024 11:00:14 +0800 [thread overview]
Message-ID: <CA+yXCZDbF9h9TXjmsSH_jO92kK4J2LVuK9ZesaiRU00TLqW2AA@mail.gmail.com> (raw)
In-Reply-To: <20240603215329.2664893-2-patrick@rivosinc.com>
Hi Patrick:
One dumb question around Zaamo and Zalrsc, could we still got correct
atomic semantic with only Zaamo or only Zalrsc? I guess Zalrsc only
probably ok, but how about Zaamo only?
And another question around authorship: I notice you are listed as
co-authored, and signed off by Edwin, but according to the mail (and
the result of git pw patch apply) the main author is you? So I'm just
curious who the main author is? not necessary to list co-authored
again if it's you, and need to update author info if it's Edwin, I
know you guy are in same the company, so that's may not big issue is
not clear, but personally I would like to mention correct authorship
if possible :P
[1] How to update author for single commit:
https://stackoverflow.com/questions/3042437/how-can-i-change-the-commit-author-for-a-single-commit
On Tue, Jun 4, 2024 at 5:54 AM Patrick O'Neill <patrick@rivosinc.com> wrote:
>
> The A extension has been split into two parts: Zaamo and Zalrsc.
> This patch adds basic support by making the A extension imply Zaamo and
> Zalrsc.
>
> Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags
> Ratification: https://jira.riscv.org/browse/RVS-1995
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc.
> * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc.
> * config/riscv/riscv.opt: Add Zaamo and Zalrsc
> * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and
> TARGET_ZALRSC.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/attribute-15.c: Adjust expected arch string.
> * gcc.target/riscv/attribute-16.c: Ditto.
> * gcc.target/riscv/attribute-17.c: Ditto.
> * gcc.target/riscv/attribute-18.c: Ditto.
> * gcc.target/riscv/pr110696.c: Ditto.
> * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto.
> * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto.
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> Co-authored-by: Patrick O'Neill <patrick@rivosinc.com>
> ---
> gcc/common/config/riscv/riscv-common.cc | 11 +++++--
> gcc/config/riscv/arch-canonicalize | 1 +
> gcc/config/riscv/riscv.opt | 6 +++-
> gcc/config/riscv/sync.md | 30 +++++++++----------
> gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +-
> gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +-
> gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr114352-1.c | 4 +--
> .../gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++---
> 11 files changed, 41 insertions(+), 29 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 88204393fde..78dfd6b1470 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
> {"f", "zicsr"},
> {"d", "zicsr"},
>
> + {"a", "zaamo"},
> + {"a", "zalrsc"},
> +
> {"zdinx", "zfinx"},
> {"zfinx", "zicsr"},
> {"zdinx", "zicsr"},
> @@ -255,6 +258,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0},
> {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
>
> {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1616,9 +1621,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
> {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND},
>
> - {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
> + {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
> {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS},
> - {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
> + {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
> + {"zaamo", &gcc_options::x_riscv_za_subext, MASK_ZAAMO},
> + {"zalrsc", &gcc_options::x_riscv_za_subext, MASK_ZALRSC},
>
> {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA},
> {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB},
> diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
> index 8f7d040cdeb..6c10d1aa81b 100755
> --- a/gcc/config/riscv/arch-canonicalize
> +++ b/gcc/config/riscv/arch-canonicalize
> @@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
> #
> IMPLIED_EXT = {
> "d" : ["f", "zicsr"],
> + "a" : ["zaamo", "zalrsc"],
> "f" : ["zicsr"],
> "zdinx" : ["zfinx", "zicsr"],
> "zfinx" : ["zicsr"],
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 87f58332016..fa57b4b1090 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -248,7 +248,11 @@ Mask(ZICCRSE) Var(riscv_zi_subext)
> TargetVariable
> int riscv_za_subext
>
> -Mask(ZAWRS) Var(riscv_za_subext)
> +Mask(ZAWRS) Var(riscv_za_subext)
> +
> +Mask(ZAAMO) Var(riscv_za_subext)
> +
> +Mask(ZALRSC) Var(riscv_za_subext)
>
> Mask(ZA64RS) Var(riscv_za_subext)
>
> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
> index 6f0b5aae08d..c9544176ead 100644
> --- a/gcc/config/riscv/sync.md
> +++ b/gcc/config/riscv/sync.md
> @@ -93,7 +93,7 @@
> (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
> (match_operand:SI 2 "const_int_operand")] ;; model
> UNSPEC_SYNC_OLD_OP))]
> - "TARGET_ATOMIC"
> + "TARGET_ZAAMO"
> "amo<insn>.<amo>%A2\tzero,%z1,%0"
> [(set_attr "type" "atomic")
> (set (attr "length") (const_int 4))])
> @@ -107,7 +107,7 @@
> (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
> (match_operand:SI 3 "const_int_operand")] ;; model
> UNSPEC_SYNC_OLD_OP))]
> - "TARGET_ATOMIC"
> + "TARGET_ZAAMO"
> "amo<insn>.<amo>%A3\t%0,%z2,%1"
> [(set_attr "type" "atomic")
> (set (attr "length") (const_int 4))])
> @@ -125,7 +125,7 @@
> (match_operand:SI 5 "register_operand" "rI") ;; not_mask
> (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1
> (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2
> - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
> {
> return "1:\;"
> "lr.w%I3\t%0, %1\;"
> @@ -144,7 +144,7 @@
> (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location
> (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op
> (match_operand:SI 3 "const_int_operand")] ;; model
> - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
> {
> /* We have no QImode/HImode atomics, so form a mask, then use
> subword_atomic_fetch_strong_nand to implement a LR/SC version of the
> @@ -192,7 +192,7 @@
> (match_operand:SI 5 "register_operand" "rI") ;; not_mask
> (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1
> (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2
> - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
> {
> return "1:\;"
> "lr.w%I3\t%0, %1\;"
> @@ -212,7 +212,7 @@
> (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location
> (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op
> (match_operand:SI 3 "const_int_operand")] ;; model
> - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
> {
> /* We have no QImode/HImode atomics, so form a mask, then use
> subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
> @@ -256,7 +256,7 @@
> UNSPEC_SYNC_EXCHANGE))
> (set (match_dup 1)
> (match_operand:GPR 2 "register_operand" "0"))]
> - "TARGET_ATOMIC"
> + "TARGET_ZAAMO"
> "amoswap.<amo>%A3\t%0,%z2,%1"
> [(set_attr "type" "atomic")
> (set (attr "length") (const_int 4))])
> @@ -266,7 +266,7 @@
> (match_operand:SHORT 1 "memory_operand") ;; mem location
> (match_operand:SHORT 2 "register_operand") ;; value
> (match_operand:SI 3 "const_int_operand")] ;; model
> - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
> {
> rtx old = gen_reg_rtx (SImode);
> rtx mem = operands[1];
> @@ -303,7 +303,7 @@
> UNSPEC_SYNC_EXCHANGE_SUBWORD))
> (match_operand:SI 4 "reg_or_0_operand" "rI") ;; not_mask
> (clobber (match_scratch:SI 5 "=&r"))] ;; tmp_1
> - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
> {
> return "1:\;"
> "lr.w%I3\t%0, %1\;"
> @@ -325,7 +325,7 @@
> (match_operand:SI 5 "const_int_operand")] ;; mod_f
> UNSPEC_COMPARE_AND_SWAP))
> (clobber (match_scratch:GPR 6 "=&r"))]
> - "TARGET_ATOMIC"
> + "TARGET_ZALRSC"
> {
> enum memmodel model_success = (enum memmodel) INTVAL (operands[4]);
> enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]);
> @@ -351,7 +351,7 @@
> (match_operand:SI 5 "const_int_operand" "") ;; is_weak
> (match_operand:SI 6 "const_int_operand" "") ;; mod_s
> (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
> - "TARGET_ATOMIC"
> + "TARGET_ZALRSC"
> {
> if (word_mode != <MODE>mode && operands[3] != const0_rtx)
> {
> @@ -394,7 +394,7 @@
> (match_operand:SI 5 "const_int_operand") ;; is_weak
> (match_operand:SI 6 "const_int_operand") ;; mod_s
> (match_operand:SI 7 "const_int_operand")] ;; mod_f
> - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
> {
> emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
> operands[3], operands[4],
> @@ -439,7 +439,7 @@
> (match_operand:SI 4 "const_int_operand") ;; mod_s
> (match_operand:SI 5 "const_int_operand") ;; mod_f
> (match_scratch:SHORT 6)]
> - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
> {
> /* We have no QImode/HImode atomics, so form a mask, then use
> subword_atomic_cas_strong<mode> to implement a LR/SC version of the
> @@ -497,7 +497,7 @@
> (match_operand:SI 5 "register_operand" "rI") ;; mask
> (match_operand:SI 6 "register_operand" "rI") ;; not_mask
> (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_1
> - "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
> + "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC"
> {
> return "1:\;"
> "lr.w%I4\t%0, %1\;"
> @@ -516,7 +516,7 @@
> [(match_operand:QI 0 "register_operand" "") ;; bool output
> (match_operand:QI 1 "memory_operand" "+A") ;; memory
> (match_operand:SI 2 "const_int_operand" "")] ;; model
> - "TARGET_ATOMIC"
> + "TARGET_ZALRSC"
> {
> /* We have no QImode atomics, so use the address LSBs to form a mask,
> then use an aligned SImode atomic. */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c
> index 59efeb6ea45..a2e394b6489 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
> @@ -3,4 +3,4 @@
> int foo()
> {
> }
> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c
> index 26f961efb48..d2b18160cb5 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-16.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c
> @@ -3,4 +3,4 @@
> int foo()
> {
> }
> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c
> index 0abff3705d9..fc2f488a3ac 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-17.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c
> @@ -3,4 +3,4 @@
> int foo()
> {
> }
> -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c
> index fddbf15fc3e..eefd602103d 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c
> @@ -1,4 +1,4 @@
> /* { dg-do compile } */
> /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */
> int foo() {}
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c
> index a630f04e74f..08682a047e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/pr110696.c
> +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
> @@ -4,4 +4,4 @@ int foo()
> {
> }
>
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
> index b3f1f20fb79..faeb406498d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
> @@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count)
> out[i] = a[i] + b[i];
> }
>
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
> index e7af4223d6a..38815ef5bd0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
> @@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count)
> out[i] = a[i] + b[i];
> }
>
> -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0" } } */
> -/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0" } } */
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */
> +/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */
> --
> 2.34.1
>
next prev parent reply other threads:[~2024-06-04 3:00 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-03 21:53 [PATCH v2 0/3] " Patrick O'Neill
2024-06-03 21:53 ` [PATCH v2 1/3] " Patrick O'Neill
2024-06-04 3:00 ` Kito Cheng [this message]
2024-06-04 17:30 ` Patrick O'Neill
2024-06-04 21:27 ` Andrew Waterman
2024-06-07 22:35 ` Jeff Law
2024-06-03 21:53 ` [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support Patrick O'Neill
2024-06-07 23:04 ` Jeff Law
2024-06-10 16:39 ` Patrick O'Neill
2024-06-11 18:21 ` Patrick O'Neill
2024-06-12 18:14 ` Jeff Law
2024-06-03 21:53 ` [PATCH v2 3/3] RISC-V: Add Zalrsc amo-op patterns Patrick O'Neill
2024-06-07 23:11 ` Jeff Law
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