From: Kito Cheng <kito.cheng@gmail.com>
To: Christoph Muellner <christoph.muellner@vrull.eu>
Cc: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Cooper Qu <cooper.qu@linux.alibaba.com>,
Lifang Xia <lifang_xia@linux.alibaba.com>,
Yunhai Shang <yunhai@linux.alibaba.com>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 05/11] riscv: Simplify output of MEM addresses
Date: Fri, 28 Apr 2023 15:21:48 +0800 [thread overview]
Message-ID: <CA+yXCZDdYRHCynxmLu6ZTSaVs0MoEeMwooCuaGWL2af+h1YE3g@mail.gmail.com> (raw)
In-Reply-To: <20230428061210.2988035-6-christoph.muellner@vrull.eu>
LGTM, thanks :)
On Fri, Apr 28, 2023 at 2:13 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> We have the following situation for MEM RTX objects:
> * TARGET_PRINT_OPERAND expands to riscv_print_operand()
> * This falls into the default case (unknown or on letter) of the outer
> switch-case-block and the MEM case of the inner switch-case-block and
> calls output_address() in final.cc with XEXP (op, 0) (the address)
> * This calls targetm.asm_out.print_operand_address() which is
> riscv_print_operand_address()
> * riscv_print_operand_address() is targeting the address of a MEM RTX
> * riscv_print_operand_address() calls riscv_print_operand() for the offset
> and directly prints the register if the address is classified as ADDRESS_REG
> * This falls into the default case (unknown or on letter) of the outer
> switch-case-block and the default case of the inner switch-case-block and
> calls output_addr_const().
>
> However, since we know that offset must be a CONST_INT (which will be
> followed by a '(<reg>)' string), there is no need to call
> riscv_print_operand() for the offset.
> Instead we can take the shortcut and use output_addr_const().
>
> This change also brings the code in riscv_print_operand_address()
> in line with the other cases, where output_addr_const() is used
> to print offsets.
>
> Tested with GCC regression test suite and SPEC intrate.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> gcc/config/riscv/riscv.cc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5d2550871c7..92043236b17 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -4581,7 +4581,7 @@ riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx
> switch (addr.type)
> {
> case ADDRESS_REG:
> - riscv_print_operand (file, addr.offset, 0);
> + output_addr_const (file, riscv_strip_unspec_address (addr.offset));
> fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
> return;
>
> --
> 2.40.1
>
next prev parent reply other threads:[~2023-04-28 7:22 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 6:12 [PATCH 00/11] Improvements for XThead* support Christoph Muellner
2023-04-28 6:12 ` [PATCH 01/11] riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extu Christoph Muellner
2023-04-28 7:17 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes Christoph Muellner
2023-04-28 7:17 ` Kito Cheng
2024-03-17 20:22 ` Christoph Müllner
2024-03-18 3:25 ` Jeff Law
2023-04-28 6:12 ` [PATCH 03/11] riscv: xtheadmempair: Fix doc for th_mempair_order_operands() Christoph Muellner
2023-04-28 7:18 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 04/11] riscv: thead: Adjust constraints of th_addsl INSN Christoph Muellner
2023-04-28 7:19 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 05/11] riscv: Simplify output of MEM addresses Christoph Muellner
2023-04-28 7:21 ` Kito Cheng [this message]
2023-04-28 6:12 ` [PATCH 06/11] riscv: Define Xmode macro Christoph Muellner
2023-04-28 7:23 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 07/11] riscv: Move address classification info types to riscv-protos.h Christoph Muellner
2023-04-28 7:23 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 08/11] riscv: Prepare backend for index registers Christoph Muellner
2023-04-28 8:34 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 09/11] riscv: thead: Factor out XThead*-specific peepholes Christoph Muellner
2023-04-28 8:37 ` Kito Cheng
2023-04-28 8:35 ` [PATCH 00/11] Improvements for XThead* support Kito Cheng
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