From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x934.google.com (mail-ua1-x934.google.com [IPv6:2607:f8b0:4864:20::934]) by sourceware.org (Postfix) with ESMTPS id 2D80B3858D37 for ; Thu, 20 Apr 2023 09:31:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2D80B3858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x934.google.com with SMTP id a1e0cc1a2514c-7782debbc94so119874241.2 for ; Thu, 20 Apr 2023 02:31:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681983072; x=1684575072; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=xbGmBkiWqfcdokER/WvKsNiBMZfvtLOLiEXQ7jhtfZU=; b=rMLegNEiEa7K6t0ysA7oFl73KSpqTKgkhbGK9DX06hXKoqNWTVYSRskjKFOVs10ZMB /otED5l13NS60eG3Ndy2Kx1d3k6E0thAM/po2DVwNCSCUYTTfaCGtyHdJyIuHvYWh2AP 91sl9lFkpdVbjjk9tqJZshXNGfZXb2qFUpT3rrtYW9OOHbkH727rRhrhYNmEIqJ1qgek xWEYWVEjkgV8A7IghToi8j5OWdlsKfU45tcYikqW2A0pwBrczPAJnpgTI9Q106NC7cEy 3qNONHcEb/HHOggHA1RleFxb9V2yyYIhWxLU1Uhc9t9fojsBoJ+uT7iSyTcTROLPUqoy /3pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681983072; x=1684575072; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xbGmBkiWqfcdokER/WvKsNiBMZfvtLOLiEXQ7jhtfZU=; b=FaY79KrO6qM6I4WSd4hgLZrS662NgKp0pcvF9bTzifsz0TZLulw8WFdfjojr7XHwLe QHCVHLjtVKc4HU/qmi2rdmL2cL38zHf/hQQadMcEDCb2m3vmRarv6LxuFg3034D1pjaf kVv/J52HwlULo4J0ZBM4Jr5u6b9V46Opje2qCSti+UgMkJTDPo7S12cA7ptKVEVY68k5 K9HN+CR461oQPbPlC3mAMEACuroHGOGsFv29N3ZNuNlWac4BXMMRhoFK5veAYMAb7/AT XwHY4UFpHe9MK43C2J6pFd9ezYLQcTVUmD/En1HUaZjefiToL7FNcQA0q5DWbBzaTimD iGZA== X-Gm-Message-State: AAQBX9csWY07hiMEzSOygzgKAz8bRlCqcTBldhKFm73e6DHSQ90MYWr8 W4ChbzKdCNMohtnHDasHcY2u8AtddujsIBsC97o= X-Google-Smtp-Source: AKy350ZAAIvmf5hf9JeGsPEGjHEuM4SYre/Miumwp0yP5kChsmpfOgEn2WN9+vKlYwcXXPzc3P0beBIA2fdXP4yBF4o= X-Received: by 2002:a67:fe8a:0:b0:42e:2b9f:f8f0 with SMTP id b10-20020a67fe8a000000b0042e2b9ff8f0mr500652vsr.30.1681983072295; Thu, 20 Apr 2023 02:31:12 -0700 (PDT) MIME-Version: 1.0 References: <20230419164214.1032017-1-juzhe.zhong@rivai.ai> <20230419164214.1032017-3-juzhe.zhong@rivai.ai> <97521df8-fdc6-a407-c156-234bdcb34cac@gmail.com> <10D3D856742B7B67+2023042017070185402754@rivai.ai> In-Reply-To: <10D3D856742B7B67+2023042017070185402754@rivai.ai> From: Kito Cheng Date: Thu, 20 Apr 2023 17:31:00 +0800 Message-ID: Subject: Re: Re: [PATCH 2/3 V2] RISC-V: Enable basic auto-vectorization for RVV To: "juzhe.zhong@rivai.ai" Cc: Robin Dapp , gcc-patches , palmer , jeffreyalaw Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Apr 20, 2023 at 5:07=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > >> With --param=3Driscv-autovec-preference=3Dfixed-vlmax, however, the ou= tput is > >> reasonable. BTW please use --param instead of -param in the descripti= on to > >> avoid confusion. > >>Now the patches don't explicitly note that they only work for certain m= archs, > >>configurations or so but they certainly shouldn't introduce ICEs for > >>unsupported configurations. > > Address comments. And fix that soon. Thank you so much. > > >>Are the "fixed-vlmax" vs "scalable" names based on ARM's SVE? I haven'= t thought > >>this through but I think I'd prefer "fixed" vs "varying" or more explic= itly > >>"fixed vector size" vs "dynamic vector size". Certainly room for discu= ssion here. > >>What about the -mriscv-vector-bits=3D... (which would be vlen in v-spec= parlance) > >>from your "rvv-next" branch? Is this orthogonal to the new parameter h= ere? Are you > >>thinking of introducing this as well? > > The current compile options are suggested by Kito. They are internal GCC = compile option. > I was trying to add -mriscv-vector-bits-...., However, it was objected by= LLVM community. > https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/33 Wait, -mriscv-vector-bits=3D isn't objected by LLVM, what they objected to is lmul option. LLVM community has try to implmenat that: https://reviews.llvm.org/D145088 But personally I would prefer not to rush to implement that feature on upst= ream, we could implement that and have more conversion with LLVM community and th= en document that into https://github.com/riscv-non-isa/rvv-intrinsic-doc or https://github.com/riscv-non-isa/riscv-toolchain-conventions > I think in case of compile options, Kito may give more comments since he = is the RISC-V ABI and convention maintainer. > I develop this patch following his order.