From: Kito Cheng <kito.cheng@gmail.com>
To: "Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>
Cc: gcc-patches@gcc.gnu.org, jim.wilson.gcc@gmail.com,
palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu,
jeffreyalaw@gmail.com, christoph.muellner@vrull.eu
Subject: Re: [PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector
Date: Sat, 18 Nov 2023 18:13:01 +0800 [thread overview]
Message-ID: <CA+yXCZDf0++uG4LyGWbcRWaAFy-3zb0x_cc58oLjAWKQP7GepA@mail.gmail.com> (raw)
In-Reply-To: <20231118042839.3651-1-cooper.joshua@linux.alibaba.com>
> diff --git a/gcc/config/riscv/riscv_th_vector.h b/gcc/config/riscv/riscv_th_vector.h
> new file mode 100644
> index 00000000000..194652032bc
> --- /dev/null
> +++ b/gcc/config/riscv/riscv_th_vector.h
...
> +/* NOTE: This implementation of riscv_vector.h is intentionally short. It does
> + not define the RVV types and intrinsic functions directly in C and C++
> + code, but instead uses the following pragma to tell GCC to insert the
> + necessary type and function definitions itself. The net effect is the
> + same, and the file is a complete implementation of riscv_vector.h. */
> +#pragma riscv intrinsic "vector"
Plz use #pragma riscv intrinsic "thead_vector"
> @@ -1135,7 +1135,7 @@ (define_expand "@mov<V_FRACT:mode><P:mode>_lra"
> [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
> (match_operand:V_FRACT 1 "reg_or_mem_operand"))
> (clobber (match_scratch:P 2))])]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
It's an accident, right?
> {})
>
> (define_expand "@mov<VB:mode><P:mode>_lra"
> @@ -1143,14 +1143,14 @@ (define_expand "@mov<VB:mode><P:mode>_lra"
> [(set (match_operand:VB 0 "reg_or_mem_operand")
> (match_operand:VB 1 "reg_or_mem_operand"))
> (clobber (match_scratch:P 2))])]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> {})
>
> (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
> [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
> (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
> (clobber (match_scratch:P 2 "=&r,&r,X"))]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> "#"
> "&& reload_completed"
> [(const_int 0)]
> @@ -1172,7 +1172,7 @@ (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
> [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
> (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
> (clobber (match_scratch:P 2 "=&r,&r,X"))]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> "#"
> "&& reload_completed"
> [(const_int 0)]
> @@ -1286,14 +1286,14 @@ (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
> [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
> (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
> (clobber (match_scratch:P 2))])]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> {})
>
> (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
> [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
> (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
> (clobber (match_scratch:P 2 "=&r,&r,X"))]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)
Ditto.
> && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
> || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
> "#"
> @@ -1359,7 +1359,7 @@ (define_expand "movmisalign<mode>"
> (define_expand "movmisalign<mode>"
> [(set (match_operand:V 0 "nonimmediate_operand")
> (match_operand:V 1 "general_operand"))]
> - "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
> + "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
Ditto.
> {
> emit_move_insn (operands[0], operands[1]);
> DONE;
> @@ -1396,7 +1396,7 @@ (define_insn_and_split "*vec_duplicate<mode>"
> [(set (match_operand:V_VLS 0 "register_operand")
> (vec_duplicate:V_VLS
> (match_operand:<VEL> 1 "direct_broadcast_operand")))]
> - "TARGET_VECTOR && can_create_pseudo_p ()"
> + "TARGET_VECTOR && can_create_pseudo_p ()"
Ditto.
> "#"
> "&& 1"
> [(const_int 0)]
next prev parent reply other threads:[~2023-11-18 10:13 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-18 4:22 [PATCH v2 0/9] RISC-V: Support XTheadVector extensions Jun Sha (Joshua)
2023-11-18 4:26 ` [PATCH v2 1/9] RISC-V: minimal support for xtheadvector Jun Sha (Joshua)
2023-11-18 10:06 ` Kito Cheng
2023-11-18 4:28 ` [PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector Jun Sha (Joshua)
2023-11-18 10:13 ` Kito Cheng [this message]
2023-11-18 4:29 ` [PATCH v2 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1) Jun Sha (Joshua)
2023-11-18 4:32 ` [PATCH v2 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2) Jun Sha (Joshua)
2023-11-18 4:34 ` [PATCH v2 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3) Jun Sha (Joshua)
2023-11-18 4:35 ` [PATCH v2 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4) Jun Sha (Joshua)
2023-11-18 4:37 ` [PATCH v2 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics Jun Sha (Joshua)
2023-11-18 4:39 ` [PATCH v2 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension Jun Sha (Joshua)
2023-12-20 12:20 ` [PATCH v3 0/6] RISC-V: Support " Jun Sha (Joshua)
2023-12-20 12:25 ` [PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc Jun Sha (Joshua)
2023-12-20 18:14 ` Jeff Law
2023-12-27 2:46 ` 回复：[PATCH " joshua
2023-12-29 1:44 ` joshua
2023-12-20 12:27 ` [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns Jun Sha (Joshua)
2023-12-20 18:16 ` Jeff Law
2023-12-27 2:49 ` 回复：[PATCH " joshua
2023-12-28 15:50 ` Jeff Law
2023-12-20 12:30 ` [PATCH v3 3/6] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2023-12-20 12:32 ` [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2023-12-20 18:22 ` Jeff Law
2023-12-20 22:48 ` 钟居哲
2023-12-21 4:41 ` Jeff Law
2023-12-21 9:43 ` Kito Cheng
2023-12-25 6:25 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-25 6:37 ` juzhe.zhong
2023-12-25 7:08 ` 回复：[PATCH " joshua
2023-12-25 7:09 ` juzhe.zhong
2023-12-25 8:14 ` [PATCH " Jun Sha (Joshua)
2023-12-25 8:18 ` juzhe.zhong
2023-12-20 12:34 ` [PATCH v3 5/6] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2023-12-20 14:00 ` 钟居哲
2023-12-20 14:24 ` 回复：[PATCH " joshua
2023-12-20 14:27 ` 钟居哲
2023-12-20 14:41 ` 回复：回复：[PATCH " joshua
2023-12-20 14:48 ` 回复：[PATCH " 钟居哲
2023-12-20 14:55 ` 钟居哲
2023-12-20 15:21 ` 回复：回复：[PATCH " joshua
2023-12-20 15:29 ` 回复：[PATCH " 钟居哲
2023-12-25 6:29 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29 1:46 ` Jun Sha (Joshua)
2023-12-29 1:58 ` juzhe.zhong
2023-12-29 2:09 ` 回复：[PATCH " joshua
2023-12-29 2:11 ` Re：[PATCH " joshua
2023-12-29 2:14 ` 回复：[PATCH " juzhe.zhong
2023-12-29 2:17 ` Re：[PATCH " joshua
2023-12-29 2:22 ` juzhe.zhong
2023-12-29 2:25 ` Re：Re：[PATCH " joshua
2023-12-29 2:25 ` Re：[PATCH " juzhe.zhong
2023-12-29 2:30 ` joshua
2023-12-29 2:31 ` juzhe.zhong
2023-12-29 2:47 ` juzhe.zhong
2023-12-20 12:36 ` [PATCH v3 6/6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2023-12-25 6:31 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29 1:49 ` Jun Sha (Joshua)
2023-12-20 23:04 ` [PATCH v3 0/6] RISC-V: Support XTheadVector extension 钟居哲
2023-12-22 3:33 ` 回复：[PATCH " joshua
2023-12-22 8:07 ` juzhe.zhong
2023-12-22 10:29 ` 回复：回复：[PATCH " joshua
2023-12-22 10:31 ` 回复：[PATCH " juzhe.zhong
2023-12-23 3:37 ` 回复：回复：[PATCH " joshua
2023-12-23 22:52 ` 回复：[PATCH " 钟居哲
2023-12-22 17:21 ` Jeff Law
2023-12-20 23:08 ` [PATCH " 钟居哲
2023-12-21 3:28 ` Jeff Law
2023-12-21 3:30 ` juzhe.zhong
2023-12-21 4:04 ` Jeff Law
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CA+yXCZDf0++uG4LyGWbcRWaAFy-3zb0x_cc58oLjAWKQP7GepA@mail.gmail.com \
--to=kito.cheng@gmail.com \
--cc=andrew@sifive.com \
--cc=christoph.muellner@vrull.eu \
--cc=cooper.joshua@linux.alibaba.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=jeffreyalaw@gmail.com \
--cc=jim.wilson.gcc@gmail.com \
--cc=palmer@dabbelt.com \
--cc=philipp.tomsich@vrull.eu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).