From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x2b.google.com (mail-oa1-x2b.google.com [IPv6:2001:4860:4864:20::2b]) by sourceware.org (Postfix) with ESMTPS id CC3003858023 for ; Sat, 18 Nov 2023 10:13:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CC3003858023 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CC3003858023 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:4860:4864:20::2b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700302397; cv=none; b=DS0ws1ucr3c+LfDY0Pfz423IBAGYvnG7jDFxhn0lUbSanK6QfvUUsHnq71KKTX+QsprBt0/DRd6xPFJujb9ubJb8vOunqxZz/tT/f7wbSpEVZjXVgKZ3+jZnPMDavSba92OfDiOBxybdZBXM1wqTCgrllSaJiVu71WV1XgX77qE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700302397; c=relaxed/simple; bh=6b2O//4O8dtxpreaAZW5HCRDS3zOWFGMmyIbyyUXW98=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=T2ozv1QOn2PthuqoFanIsuUOWAKG4T6gNpv/5epaH+JOTIX8pm2m59Svh7EmCUXZDOXXatDegNugR4lK9Zc39ZSgXGSjis6opEWD7HBOA60eFmNXOrkKMn7fLdp4wedl8ACWfL/jPZM8Ec8XxJcaGa7DBbAt+7Exeelvw6aP6cQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-1f066fc2a2aso1324313fac.0 for ; Sat, 18 Nov 2023 02:13:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700302395; x=1700907195; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=TSBybmnY4SqQZQ0KYNHIL6BZKTDnT27ijQKG3IgjnK4=; b=ccFFuqoT9neUqpWGrezJ0LcGdKMZoJ4uy52fdVbb6korFr7S22umvcIerPhdGaHs+U r2pfrdAEavtFBACTd8qylqEgwvHJhICIFEaWb80Ng4rkpP1keXlGQu11Dz+cVzc8IepI rvDyjpXSzpoWGIbIio8Dmk9VMJb41Ps5n8t07xu4TkLabQHHQQE+hW4VUBUtETWm2R31 4KwHWnRDmPNrHzSXd1mWpf7SWqWrcLkaYIy3tGZs1lOpWu1tvEfjuy8/wIyy45eEKfr5 xOe6v9NO5TxFSpIaWRBw0YOjyXC+jxKifvpeK+C3h0kfnfELm2A5xTQCAFNlJNzzrTSx vclw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700302395; x=1700907195; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=TSBybmnY4SqQZQ0KYNHIL6BZKTDnT27ijQKG3IgjnK4=; b=gncUeilDRta35/pt30L2QasLWDioUHCiOcumUaYIRAUieB386XS90voWTD58C9Al5P EJiUx0g/BnzioPjhGnwdLneNbMk2HQ9SCMtnxH0H6M3ZAxHCvL36UHbZHv/855hU2VXC rO1/vB1iu1838RqbhPkJROM5hXxpVfqVfdfFCYnIjFtNzryraB/bJloCcRnMNN2whbUY rvLijFZO27qIr4k75vci9dV8wt0ew8UH+lRRyPlDnvcupFuz0jv0M+nMM36Ddp5pmjBO s0ZxojKibp2pRl5h6x4UIxxWiA2q2af4KzkGsz8nrFMdDE3AAR30XsAu3CBcr6OyVVdz QFxw== X-Gm-Message-State: AOJu0YxeW0cS2/qBTP1Ivhtkze1Jp+VHwfuhiMstZr/DlPQ+1lJTj8Q7 AZhzufvs/O4Nr5BO4fJxxBWlR+pS38nSsgLOmWE= X-Google-Smtp-Source: AGHT+IEMOfYeSe85UroEYteEy3a6rC5SpVBsDvj/E0AOhR/PWkKb58MxPwZiNHpkEWU2aPQ2dhow7PkrgfOIid1s6Rk= X-Received: by 2002:a05:6870:7d18:b0:1f4:d990:fb41 with SMTP id os24-20020a0568707d1800b001f4d990fb41mr1725404oab.59.1700302394946; Sat, 18 Nov 2023 02:13:14 -0800 (PST) MIME-Version: 1.0 References: <20231118042258.3545-1-cooper.joshua@linux.alibaba.com> <20231118042839.3651-1-cooper.joshua@linux.alibaba.com> In-Reply-To: <20231118042839.3651-1-cooper.joshua@linux.alibaba.com> From: Kito Cheng Date: Sat, 18 Nov 2023 18:13:01 +0800 Message-ID: Subject: Re: [PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector To: "Jun Sha (Joshua)" Cc: gcc-patches@gcc.gnu.org, jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > diff --git a/gcc/config/riscv/riscv_th_vector.h b/gcc/config/riscv/riscv_th_vector.h > new file mode 100644 > index 00000000000..194652032bc > --- /dev/null > +++ b/gcc/config/riscv/riscv_th_vector.h ... > +/* NOTE: This implementation of riscv_vector.h is intentionally short. It does > + not define the RVV types and intrinsic functions directly in C and C++ > + code, but instead uses the following pragma to tell GCC to insert the > + necessary type and function definitions itself. The net effect is the > + same, and the file is a complete implementation of riscv_vector.h. */ > +#pragma riscv intrinsic "vector" Plz use #pragma riscv intrinsic "thead_vector" > @@ -1135,7 +1135,7 @@ (define_expand "@mov_lra" > [(set (match_operand:V_FRACT 0 "reg_or_mem_operand") > (match_operand:V_FRACT 1 "reg_or_mem_operand")) > (clobber (match_scratch:P 2))])] > - "TARGET_VECTOR && (lra_in_progress || reload_completed)" > + "TARGET_VECTOR && (lra_in_progress || reload_completed)" It's an accident, right? > {}) > > (define_expand "@mov_lra" > @@ -1143,14 +1143,14 @@ (define_expand "@mov_lra" > [(set (match_operand:VB 0 "reg_or_mem_operand") > (match_operand:VB 1 "reg_or_mem_operand")) > (clobber (match_scratch:P 2))])] > - "TARGET_VECTOR && (lra_in_progress || reload_completed)" > + "TARGET_VECTOR && (lra_in_progress || reload_completed)" Ditto. > {}) > > (define_insn_and_split "*mov_lra" > [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr") > (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr")) > (clobber (match_scratch:P 2 "=&r,&r,X"))] > - "TARGET_VECTOR && (lra_in_progress || reload_completed)" > + "TARGET_VECTOR && (lra_in_progress || reload_completed)" Ditto. > "#" > "&& reload_completed" > [(const_int 0)] > @@ -1172,7 +1172,7 @@ (define_insn_and_split "*mov_lra" > [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr") > (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr")) > (clobber (match_scratch:P 2 "=&r,&r,X"))] > - "TARGET_VECTOR && (lra_in_progress || reload_completed)" > + "TARGET_VECTOR && (lra_in_progress || reload_completed)" Ditto. > "#" > "&& reload_completed" > [(const_int 0)] > @@ -1286,14 +1286,14 @@ (define_expand "@mov_lra" > [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand") > (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand")) > (clobber (match_scratch:P 2))])] > - "TARGET_VECTOR && (lra_in_progress || reload_completed)" > + "TARGET_VECTOR && (lra_in_progress || reload_completed)" Ditto. > {}) > > (define_insn_and_split "*mov_lra" > [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr") > (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr")) > (clobber (match_scratch:P 2 "=&r,&r,X"))] > - "TARGET_VECTOR && (lra_in_progress || reload_completed) > + "TARGET_VECTOR && (lra_in_progress || reload_completed) Ditto. > && (register_operand (operands[0], mode) > || register_operand (operands[1], mode))" > "#" > @@ -1359,7 +1359,7 @@ (define_expand "movmisalign" > (define_expand "movmisalign" > [(set (match_operand:V 0 "nonimmediate_operand") > (match_operand:V 1 "general_operand"))] > - "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED" > + "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED" Ditto. > { > emit_move_insn (operands[0], operands[1]); > DONE; > @@ -1396,7 +1396,7 @@ (define_insn_and_split "*vec_duplicate" > [(set (match_operand:V_VLS 0 "register_operand") > (vec_duplicate:V_VLS > (match_operand: 1 "direct_broadcast_operand")))] > - "TARGET_VECTOR && can_create_pseudo_p ()" > + "TARGET_VECTOR && can_create_pseudo_p ()" Ditto. > "#" > "&& 1" > [(const_int 0)]