Re: [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0

[Kito Cheng <kito.cheng@gmail.com>]

LGTM

On Fri, Jan 12, 2024 at 3:32 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> This patch needs kito review. I can't approve that.
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Jun Sha (Joshua)
> Date: 2024-01-12 11:20
> To: gcc-patches
> CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; kito.cheng; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
> Subject: [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
> This patch is to introduce basic XTheadVector support
> (march string parsing and a test for __riscv_xtheadvector)
> according to https://github.com/T-head-Semi/thead-extension-spec/
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc
> (riscv_subset_list::parse): Add new vendor extension.
> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
> Add test marco.
> * config/riscv/riscv.opt:  Add new mask.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
> * gcc.target/riscv/rvv/xtheadvector.c: New test.
>
> Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> gcc/common/config/riscv/riscv-common.cc       | 23 +++++++++++++++++++
> gcc/config/riscv/riscv-c.cc                   |  8 +++++--
> gcc/config/riscv/riscv.opt                    |  2 ++
> .../riscv/predef-__riscv_th_v_intrinsic.c     | 11 +++++++++
> .../gcc.target/riscv/rvv/xtheadvector.c       | 13 +++++++++++
> 5 files changed, 55 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 0301d170a41..449722070d4 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -368,6 +368,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1251,6 +1252,15 @@ riscv_subset_list::check_conflict_ext ()
>        if (lookup ("zcmp"))
> error_at (m_loc, "%<-march=%s%>: zcd conflicts with zcmp", m_arch);
>      }
> +
> +  if ((lookup ("v") || lookup ("zve32x")
> + || lookup ("zve64x") || lookup ("zve32f")
> + || lookup ("zve64f") || lookup ("zve64d")
> + || lookup ("zvl32b") || lookup ("zvl64b")
> + || lookup ("zvl128b") || lookup ("zvfh"))
> + && lookup ("xtheadvector"))
> +    error_at (m_loc, "%<-march=%s%>: xtheadvector conflicts with vector "
> +    "extension or its sub-extensions", m_arch);
> }
> /* Parsing function for multi-letter extensions.
> @@ -1743,6 +1753,19 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
>    {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
>    {"xtheadsync",    &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
> +  {"xtheadvector",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
> +  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32},
> +  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
> +  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32},
> +  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64},
> +  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16},
> +  {"xtheadvector",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B},
> +  {"xtheadvector",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B},
> +  {"xtheadvector",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL128B},
> +  {"xtheadvector",  &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
> +  {"xtheadvector",  &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
> +  {"xtheadvector",  &gcc_options::x_target_flags, MASK_FULL_V},
> +  {"xtheadvector",  &gcc_options::x_target_flags, MASK_VECTOR},
>    {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> index ba60cd8b555..422ddc2c308 100644
> --- a/gcc/config/riscv/riscv-c.cc
> +++ b/gcc/config/riscv/riscv-c.cc
> @@ -142,6 +142,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
>      riscv_ext_version_value (0, 11));
>      }
> +   if (TARGET_XTHEADVECTOR)
> +     builtin_define_with_int_value ("__riscv_th_v_intrinsic",
> +      riscv_ext_version_value (0, 11));
> +
>    /* Define architecture extension test macros.  */
>    builtin_define_with_int_value ("__riscv_arch_test", 1);
> @@ -195,8 +199,8 @@ riscv_pragma_intrinsic (cpp_reader *)
>      {
>        if (!TARGET_VECTOR)
> {
> -   error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
> - "enabled",
> +   error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
> + "'XTHEADVECTOR' extension enabled",
> name);
>   return;
> }
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 44ed6d69da2..bb18a22b693 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -452,6 +452,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
> Mask(XTHEADSYNC)    Var(riscv_xthead_subext)
> +Mask(XTHEADVECTOR)  Var(riscv_xthead_subext)
> +
> TargetVariable
> int riscv_xventana_subext
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
> new file mode 100644
> index 00000000000..550b9039a06
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64imafdcxtheadvector -mabi=lp64d" } */
> +
> +int main () {
> +
> +#if __riscv_th_v_intrinsic != 11000
> +#error "__riscv_th_v_intrinsic"
> +#endif
> +
> +  return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
> new file mode 100644
> index 00000000000..8ad370172e3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_xtheadvector" { target { rv32 } } } */
> +/* { dg-options "-march=rv64gc_xtheadvector" { target { rv64 } } } */
> +
> +#ifndef __riscv_xtheadvector
> +#error "Feature macro not defined"
> +#endif
> +
> +int
> +foo (int a)
> +{
> +  return a;
> +}
> --
> 2.17.1
>
>