From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id BC7033858D33 for ; Thu, 18 Jan 2024 09:51:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BC7033858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BC7033858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::630 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705571465; cv=none; b=KcfZYDejKWYtbtRL6bGnMi0tQI9iKDVLvZjAqXNLBKCvyB5TVHytPNW2s7hz5anIIStWBzlLsLn7XiCrlS2cK7vqg1ZvOs1oJoV/ZuqsiYkEw1WD4w9ffwENB6/Y0cHoG7CAiG4rY0PNaP4JOS21EX0r+3ER4I4fJvgsi41d7DU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1705571465; c=relaxed/simple; bh=JcVJ5uSK7+zVz3IvUglRUiR7AVeieQn8YRAjcUBraxs=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=M79WRwzCc0TZ9JZHG3QcSWojhGNntichJs1dxFuQ46TJ/10Giiq2+5p3YDAbUdCT6oGtc5BYu9FiqTDuRstOIx6+SBYM1cpNvi4klr2X3gcRVIcL/kBJzLZY735gHo0tA6gaIulk7R0EjCuoal7+mMVdX+MCWarxCYj2g9LRQdY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a28cc85e6b5so1429519166b.1 for ; Thu, 18 Jan 2024 01:51:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1705571460; x=1706176260; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=+tuOTOEVMNgwb0IW3sRluuY+BSZkMxRoMlYfF//6Jus=; b=V13WzoWv5FXX7knER2h/REc70Ox1QebEoLCQJEkfzuqP4UribsR2dLDZbSO6Uag+0j mPtc7UhKciZIxJ38yHTlhFthaiB5QvZ4VtiCo3grwXIxv5FuqduAgK8MxLLWhLvL9936 VVUgKW5Pr/JRXwcFmHDi877HenDcD5Cm0JNelF74MTxu3TObGXcBqCuT4aUcznNHka0+ PCfHWg2GsTI5qWryausz07X+tlKI4o8jfYjCwxa4bcV9TNFjokuLLx2LF/W0iVe//QhK 44ke8CZn28NkjOokKtFk+3K9tcPmPQWcTdWXN+ULWxD8Deo37Jp2lXvdjsY1x4gBEUrI 66pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705571460; x=1706176260; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+tuOTOEVMNgwb0IW3sRluuY+BSZkMxRoMlYfF//6Jus=; b=u4ELDKUpw+El4XSHyx3xI7FCTlviVdfBwDk7lEkzRS1Wa0Kw/j1B3JDUGG1tVaLxA2 5OzSqzo08RDMP971sB+zBTKBOB1Co/8NxGyG5JIVO9hEe3ASle9EvQpcyN3QJazicwuB 8sc5ZQIDKYQVDACnHG28Eqi65NcUbFp9zMKczxG+/9B9GZEJF7kokGlK1l7/mVxIBoNE fg2GY5zYzxhgVp8xjQFl30nT2M+4yaDlFInG6UIrhMJ9qVRzRg37yJGvFAz+8x9WnwP8 hb8w6TL1+dWnppYli4ImfVXBlL6T+3A8PRjrPQIHAoxBOzU81dNONRdKEGH8xR4MJn8Z mRgw== X-Gm-Message-State: AOJu0YyDyf5yMaRcQV90JO18c2rwm/mTu7z0/2i2eXzNorLt1Ie/ME/y TugSNlgpuoJxGwh73a7efMlvB0WLbyfDJn9CikplPUBqdiQ/6LA8iTTRH8HaKKlxAOrHaJEQbHq mVlqUG2SMBXo4WCj5PPomBEcZ8O4= X-Google-Smtp-Source: AGHT+IEGKUSWDIzPfn7p8zwNEDi2WSNqE0BcDTQPDQw1uvnSQY3ao7Tm+dj0roqLN/mfJgdRpGjk+Lzw2C/Ls9UB7OY= X-Received: by 2002:a17:906:6a17:b0:a2e:7d16:9f81 with SMTP id qw23-20020a1709066a1700b00a2e7d169f81mr283296ejc.228.1705571460065; Thu, 18 Jan 2024 01:51:00 -0800 (PST) MIME-Version: 1.0 References: <20240112031840.1556-1-cooper.joshua@linux.alibaba.com> <20240112032029.1609-1-cooper.joshua@linux.alibaba.com> <313FCBD1DE5DEB2B+202401121531156877111@rivai.ai> In-Reply-To: <313FCBD1DE5DEB2B+202401121531156877111@rivai.ai> From: Kito Cheng Date: Thu, 18 Jan 2024 17:50:47 +0800 Message-ID: Subject: Re: [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 To: "juzhe.zhong@rivai.ai" Cc: "cooper.joshua" , gcc-patches , Jim Wilson , palmer , andrew , "philipp.tomsich" , jeffreyalaw , "christoph.muellner" , jinma , "cooper.qu" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Fri, Jan 12, 2024 at 3:32=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > This patch needs kito review. I can't approve that. > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Jun Sha (Joshua) > Date: 2024-01-12 11:20 > To: gcc-patches > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christo= ph.muellner; juzhe.zhong; kito.cheng; Jun Sha (Joshua); Jin Ma; Xianmiao Qu > Subject: [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 > This patch is to introduce basic XTheadVector support > (march string parsing and a test for __riscv_xtheadvector) > according to https://github.com/T-head-Semi/thead-extension-spec/ > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc > (riscv_subset_list::parse): Add new vendor extension. > * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): > Add test marco. > * config/riscv/riscv.opt: Add new mask. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test. > * gcc.target/riscv/rvv/xtheadvector.c: New test. > > Co-authored-by: Jin Ma > Co-authored-by: Xianmiao Qu > Co-authored-by: Christoph M=C3=BCllner > --- > gcc/common/config/riscv/riscv-common.cc | 23 +++++++++++++++++++ > gcc/config/riscv/riscv-c.cc | 8 +++++-- > gcc/config/riscv/riscv.opt | 2 ++ > .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +++++++++ > .../gcc.target/riscv/rvv/xtheadvector.c | 13 +++++++++++ > 5 files changed, 55 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_int= rinsic.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/= riscv/riscv-common.cc > index 0301d170a41..449722070d4 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -368,6 +368,7 @@ static const struct riscv_ext_version riscv_ext_versi= on_table[] =3D > {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, > @@ -1251,6 +1252,15 @@ riscv_subset_list::check_conflict_ext () > if (lookup ("zcmp")) > error_at (m_loc, "%<-march=3D%s%>: zcd conflicts with zcmp", m_arch); > } > + > + if ((lookup ("v") || lookup ("zve32x") > + || lookup ("zve64x") || lookup ("zve32f") > + || lookup ("zve64f") || lookup ("zve64d") > + || lookup ("zvl32b") || lookup ("zvl64b") > + || lookup ("zvl128b") || lookup ("zvfh")) > + && lookup ("xtheadvector")) > + error_at (m_loc, "%<-march=3D%s%>: xtheadvector conflicts with vecto= r " > + "extension or its sub-extensions", m_arch); > } > /* Parsing function for multi-letter extensions. > @@ -1743,6 +1753,19 @@ static const riscv_ext_flag_table_t riscv_ext_flag= _table[] =3D > {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMI= DX}, > {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMP= AIR}, > {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC= }, > + {"xtheadvector", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECT= OR}, > + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR= _ELEN_32}, > + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR= _ELEN_64}, > + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR= _ELEN_FP_32}, > + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR= _ELEN_FP_64}, > + {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR= _ELEN_FP_16}, > + {"xtheadvector", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B}, > + {"xtheadvector", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B}, > + {"xtheadvector", &gcc_options::x_riscv_zvl_flags, MASK_ZVL128B}, > + {"xtheadvector", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN}, > + {"xtheadvector", &gcc_options::x_riscv_zf_subext, MASK_ZVFH}, > + {"xtheadvector", &gcc_options::x_target_flags, MASK_FULL_V}, > + {"xtheadvector", &gcc_options::x_target_flags, MASK_VECTOR}, > {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTA= NACONDOPS}, > diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc > index ba60cd8b555..422ddc2c308 100644 > --- a/gcc/config/riscv/riscv-c.cc > +++ b/gcc/config/riscv/riscv-c.cc > @@ -142,6 +142,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) > riscv_ext_version_value (0, 11)); > } > + if (TARGET_XTHEADVECTOR) > + builtin_define_with_int_value ("__riscv_th_v_intrinsic", > + riscv_ext_version_value (0, 11)); > + > /* Define architecture extension test macros. */ > builtin_define_with_int_value ("__riscv_arch_test", 1); > @@ -195,8 +199,8 @@ riscv_pragma_intrinsic (cpp_reader *) > { > if (!TARGET_VECTOR) > { > - error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension " > - "enabled", > + error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or " > + "'XTHEADVECTOR' extension enabled", > name); > return; > } > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 44ed6d69da2..bb18a22b693 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -452,6 +452,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) > Mask(XTHEADSYNC) Var(riscv_xthead_subext) > +Mask(XTHEADVECTOR) Var(riscv_xthead_subext) > + > TargetVariable > int riscv_xventana_subext > diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic= .c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c > new file mode 100644 > index 00000000000..550b9039a06 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64imafdcxtheadvector -mabi=3Dlp64d" } */ > + > +int main () { > + > +#if __riscv_th_v_intrinsic !=3D 11000 > +#error "__riscv_th_v_intrinsic" > +#endif > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c b/gcc/test= suite/gcc.target/riscv/rvv/xtheadvector.c > new file mode 100644 > index 00000000000..8ad370172e3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c > @@ -0,0 +1,13 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gc_xtheadvector" { target { rv32 } } } */ > +/* { dg-options "-march=3Drv64gc_xtheadvector" { target { rv64 } } } */ > + > +#ifndef __riscv_xtheadvector > +#error "Feature macro not defined" > +#endif > + > +int > +foo (int a) > +{ > + return a; > +} > -- > 2.17.1 > >