From: Kito Cheng <kito.cheng@gmail.com>
To: shiyulong@iscas.ac.cn
Cc: "GCC Patches" <gcc-patches@gcc.gnu.org>,
"Andrew Waterman" <andrew@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Jim Wilson" <jim.wilson.gcc@gmail.com>,
wuwei2016@iscas.ac.cn, jiawei <jiawei@iscas.ac.cn>,
廖仕华 <shihua@iscas.ac.cn>, "Sinan Lin" <sinan@isrc.iscas.ac.cn>
Subject: Re: [PATCH V3 2/3] RISC-V:Cache Management Operation instructions
Date: Mon, 9 May 2022 19:01:03 +0800 [thread overview]
Message-ID: <CA+yXCZDmsYEYe-RNEa6-S69bT1CbUTW2VtVzQJ9Ni60dUhLuDA@mail.gmail.com> (raw)
In-Reply-To: <20220509022939.21636-3-shiyulong@iscas.ac.cn>
Use unspec_volatile instead of unspec for those cache operations,
because those operations have side effects, instruction scheduler
might reorder those CMO operations if you use unspec.
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index b3c5bce842a..d60843df490 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -45,6 +45,11 @@
>
> ;; Stack tie
> UNSPEC_TIE
> + UNSPEC_CLEAN
> + UNSPEC_FLUSH
> + UNSPEC_INVAL
> + UNSPEC_ZERO
> + UNSPEC_PREI
And then move those UNSPEC to unspecv
> ])
>
> (define_c_enum "unspecv" [
> @@ -69,6 +74,7 @@
> ;; Stack Smash Protector
> UNSPEC_SSP_SET
> UNSPEC_SSP_TEST
> +
> ])
next prev parent reply other threads:[~2022-05-09 11:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-09 2:29 [PATCH V3 0/3] RISC-V:Add mininal support for Zicbo[mzp] shiyulong
2022-05-09 2:29 ` [PATCH V3 1/3] RISC-V: Add " shiyulong
2022-05-09 2:29 ` [PATCH V3 2/3] RISC-V:Cache Management Operation instructions shiyulong
2022-05-09 11:01 ` Kito Cheng [this message]
2022-05-09 2:29 ` [PATCH V3 3/3] RISC-V:Cache Management Operation instructions testcases shiyulong
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