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Tue, 05 Dec 2023 07:11:57 -0800 (PST) MIME-Version: 1.0 References: <20231113133530.1727444-1-mary.bennett@embecosm.com> <20231128131615.3986922-1-mary.bennett@embecosm.com> <20231128131615.3986922-2-mary.bennett@embecosm.com> In-Reply-To: <20231128131615.3986922-2-mary.bennett@embecosm.com> From: Kito Cheng Date: Tue, 5 Dec 2023 23:11:45 +0800 Message-ID: Subject: Re: [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P To: Mary Bennett Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Tue, Nov 28, 2023 at 9:17=E2=80=AFPM Mary Bennett wrote: > > Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-b= uiltin-spec.md > > Contributors: > Mary Bennett > Nandni Jamnadas > Pietra Ferreira > Charlie Keaney > Jessica Mills > Craig Blackmore > Simon Cook > Jeremy Bennett > Helene Chelin > > gcc/ChangeLog: > * common/config/riscv/riscv-common.cc: Add XCVelw. > * config/riscv/corev.def: Likewise. > * config/riscv/corev.md: Likewise. > * config/riscv/riscv-builtins.cc (AVAIL): Likewise. > * config/riscv/riscv-ftypes.def: Likewise. > * config/riscv/riscv.opt: Likewise. > * doc/extend.texi: Add XCVelw builtin documentation. > * doc/sourcebuild.texi: Likewise. > > gcc/testsuite/ChangeLog: > * gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw. > * testsuite/lib/target-supports.exp: Add proc for the XCVelw exte= nsion. > --- > gcc/common/config/riscv/riscv-common.cc | 2 ++ > gcc/config/riscv/corev.def | 3 +++ > gcc/config/riscv/corev.md | 15 +++++++++++++++ > gcc/config/riscv/riscv-builtins.cc | 2 ++ > gcc/config/riscv/riscv-ftypes.def | 1 + > gcc/config/riscv/riscv.opt | 2 ++ > gcc/doc/extend.texi | 8 ++++++++ > gcc/doc/sourcebuild.texi | 3 +++ > .../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++++++++ > gcc/testsuite/lib/target-supports.exp | 13 +++++++++++++ > 10 files changed, 60 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/= riscv/riscv-common.cc > index 5111626157b..c8c0d0a2252 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -312,6 +312,7 @@ static const struct riscv_ext_version riscv_ext_versi= on_table[] =3D > > {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, > > {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, > @@ -1676,6 +1677,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_= table[] =3D > > {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC}, > {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU}, > + {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW}, > > {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, > {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, > diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def > index 17580df3c41..3b9ec029d06 100644 > --- a/gcc/config/riscv/corev.def > +++ b/gcc/config/riscv/corev.def > @@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", RISCV_BU= ILTIN_DIRECT, RISCV_SI_FT > RISCV_BUILTIN (cv_alu_subuN, "cv_alu_subuN", RISCV_BUILTIN_DIRECT, RI= SCV_USI_FTYPE_USI_USI_UQI, cvalu), > RISCV_BUILTIN (cv_alu_subRN, "cv_alu_subRN", RISCV_BUILTIN_DIRECT, RI= SCV_SI_FTYPE_SI_SI_UQI, cvalu), > RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RI= SCV_USI_FTYPE_USI_USI_UQI, cvalu), > + > +// XCVELW > +RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_= USI_FTYPE_VOID_PTR, cvelw), > diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md > index 1350bd4b81e..c7a2ba07bcc 100644 > --- a/gcc/config/riscv/corev.md > +++ b/gcc/config/riscv/corev.md > @@ -24,6 +24,9 @@ > UNSPEC_CV_ALU_CLIPR > UNSPEC_CV_ALU_CLIPU > UNSPEC_CV_ALU_CLIPUR > + > + ;;CORE-V EVENT LOAD > + UNSPECV_CV_ELW > ]) > > ;; XCVMAC extension. > @@ -691,3 +694,15 @@ > cv.suburnr\t%0,%2,%3" > [(set_attr "type" "arith") > (set_attr "mode" "SI")]) > + > +;; XCVELW builtins > +(define_insn "riscv_cv_elw_elw_si" > + [(set (match_operand:SI 0 "register_operand" "=3Dr") > + (unspec_volatile [(match_operand:SI 1 "move_operand" "p")] > + UNSPECV_CV_ELW))] > + > + "TARGET_XCVELW && !TARGET_64BIT" > + "cv.elw\t%0,%a1" > + > + [(set_attr "type" "load") > + (set_attr "mode" "SI")]) > diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-= builtins.cc > index fc3976f3ba1..5ee11ebe3bc 100644 > --- a/gcc/config/riscv/riscv-builtins.cc > +++ b/gcc/config/riscv/riscv-builtins.cc > @@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0)) > // CORE-V AVAIL > AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT) > AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) > +AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT) > > /* Construct a riscv_builtin_description from the given arguments. > > @@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) > #define RISCV_ATYPE_HI intHI_type_node > #define RISCV_ATYPE_SI intSI_type_node > #define RISCV_ATYPE_VOID_PTR ptr_type_node > +#define RISCV_ATYPE_INT_PTR integer_ptr_type_node > > /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists > their associated RISCV_ATYPEs. */ > diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-f= types.def > index 0d1e4dd061e..3e7d5c69503 100644 > --- a/gcc/config/riscv/riscv-ftypes.def > +++ b/gcc/config/riscv/riscv-ftypes.def > @@ -30,6 +30,7 @@ DEF_RISCV_FTYPE (0, (USI)) > DEF_RISCV_FTYPE (0, (VOID)) > DEF_RISCV_FTYPE (1, (VOID, USI)) > DEF_RISCV_FTYPE (1, (VOID, VOID_PTR)) > +DEF_RISCV_FTYPE (1, (USI, VOID_PTR)) > DEF_RISCV_FTYPE (1, (USI, USI)) > DEF_RISCV_FTYPE (1, (UDI, UDI)) > DEF_RISCV_FTYPE (1, (USI, UQI)) > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 11526f9cc2a..bfa0945daca 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -411,6 +411,8 @@ Mask(XCVMAC) Var(riscv_xcv_subext) > > Mask(XCVALU) Var(riscv_xcv_subext) > > +Mask(XCVELW) Var(riscv_xcv_subext) > + > TargetVariable > int riscv_xthead_subext > > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index 9474e9398bb..b89aa915b7e 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -22084,6 +22084,14 @@ Generated assembler @code{cv.subuRN} if the uint= 8_t operand is a constant and in > Generated assembler @code{cv.subuRNr} if the it is a register. > @end deftypefn > > +These built-in functions are available for the CORE-V Event Load machine > +architecture. For more information on CORE-V ELW builtins, please see > +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specification= s/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw} > + > +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_elw_elw (ui= nt32_t *) > +Generated assembler @code{cv.elw} > +@end deftypefn > + > @node RX Built-in Functions > @subsection RX Built-in Functions > GCC supports some of the RX instructions which cannot be expressed in > diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi > index e27e0fa606c..d63b11d245c 100644 > --- a/gcc/doc/sourcebuild.texi > +++ b/gcc/doc/sourcebuild.texi > @@ -2481,6 +2481,9 @@ Test system has support for the CORE-V MAC extensio= n. > @item cv_alu > Test system has support for the CORE-V ALU extension. > > +@item cv_elw > +Test system has support for the CORE-V ELW extension. > + > @end table > > @subsubsection Other hardware attributes > diff --git a/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c b/gcc/= testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c > new file mode 100644 > index 00000000000..30f951c3f0a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target cv_elw } */ > +/* { dg-options "-march=3Drv32i_xcvelw -mabi=3Dilp32" } */ > + > +int > +foo (void* b) > +{ > + return __builtin_riscv_cv_elw_elw (b + 8); > +} > + > +/* { dg-final { scan-assembler-times "cv\\.elw\t\[a-z\]\[0-99\],\[0-99\]= \\(\[a-z\]\[0-99\]\\)" 1 } } */ > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/ta= rget-supports.exp > index 87b2ae58720..c324a7898fc 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -13147,6 +13147,19 @@ proc check_effective_target_cv_alu { } { > } "-march=3Drv32i_xcvalu" ] > } > > +# Return 1 if the CORE-V ELW extension is available. > +proc check_effective_target_cv_elw { } { > + if { !([istarget riscv*-*-*]) } { > + return 0 > + } > + return [check_no_compiler_messages cv_elw object { > + void foo (void) > + { > + asm ("cv.elw x0, 0(x0)"); > + } > + } "-march=3Drv32i_xcvelw" ] > +} > + > proc check_effective_target_loongarch_sx { } { > return [check_no_compiler_messages loongarch_lsx assembly { > #if !defined(__loongarch_sx) > -- > 2.34.1 >