From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2a.google.com (mail-vs1-xe2a.google.com [IPv6:2607:f8b0:4864:20::e2a]) by sourceware.org (Postfix) with ESMTPS id 5ADFF3858D20 for ; Wed, 20 Sep 2023 00:52:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5ADFF3858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2a.google.com with SMTP id ada2fe7eead31-45260b91a29so1464868137.2 for ; Tue, 19 Sep 2023 17:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695171163; x=1695775963; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=0GOOyE85p0AEEpAfs0ZqKFxyKtjdoPRfsRBiHUA4SZo=; b=gazoQr+5DGd61mawc0x2GjxLhfS/XFvtuM9IM2hu7+sSXuZGM90JDHJcacgneHZR4X 0X0bBZv/Q27d/hj0kd22PR0Tb618bNwUKKxVZLMNnp9AA7MB2oJWq4wZrdrshmMT5Fit pcnXaYDsmFUEDH58WjuYYyFCKbauSX2bMg+0exLPFTU/l4SIGyO9C1ZyPVVUqZ9NWW4D f1sQBEFbxtapDE01wWgznn//wlytD/ZXpDkvyGOJiB9gAjv8HstLQWgJiNuazrIypxLl yueioxwHOHhX1hP7OTTWvE33sGCV7NirGUsZDUEhrioyOOUIH7oTZDxvtXQPzFKdU1XV boBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695171163; x=1695775963; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=0GOOyE85p0AEEpAfs0ZqKFxyKtjdoPRfsRBiHUA4SZo=; b=gv4HcePaDkEDl7TDqTuAoP1IWxaCMpGYqO4qLrURVzpdtG6EMcod71dvToniNnV7w+ L46HljJji7y2u4cM3ynxc4+WomIXljS3tkM8LTOCwZipL6wtRB4helBVu1loHQ4Ickv3 nqO62l0J8NmIe5449EoP5+KtUfBB5JGAtBrOQiOuWHfP0pMUvdTiTJfMQOnKZAkkIlYC 2WccodRTyaxnJHgeZ2N6vA+cLacXOTFO28ZcOi657v5Mggf+nlm0bcYTAG7n+J41AfCO ltQIEW1FUsh5Wx6tKgPqXbWQrbfd4Ua7oWFhULfNxeJqo5RdW7d8YYkKxbfrr+BqxIOx 3icQ== X-Gm-Message-State: AOJu0Yz620Os054x29MLbPG4N0gFD7agEiqTHg/I+/Z/BQ3av7uMEksh plPCIyos+sPTn1e2QyijIKyN9ZGtL0q5pZYvmks= X-Google-Smtp-Source: AGHT+IFvPaeKft4QSgemkB6woUWL8XTUy8+OPH+jYU1eFmhTX1iyvulbSjxWmQ8Sn/1fVchSKvrd6qxtJIGBB6lcwAc= X-Received: by 2002:a67:f1ce:0:b0:452:82c4:d641 with SMTP id v14-20020a67f1ce000000b0045282c4d641mr1584297vsm.31.1695171162973; Tue, 19 Sep 2023 17:52:42 -0700 (PDT) MIME-Version: 1.0 References: <20230919112653.539780-1-juzhe.zhong@rivai.ai> <093b0e09-6106-447b-f8f8-0c036f2c927b@rivosinc.com> In-Reply-To: From: Kito Cheng Date: Wed, 20 Sep 2023 08:52:31 +0800 Message-ID: Subject: Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns To: =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: "Patrick O'Neill" , Robin Dapp , gcc-patches , "Kito.cheng" , jeffreyalaw , palmer , Edwin Lu , "joern.rennecke" , "jeremy.bennett" , gnu-toolchain Content-Type: multipart/alternative; boundary="00000000000000aae50605bfcbf5" X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000000aae50605bfcbf5 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable It seems because math.h, similar issue as stdint.h, does math.h necessary for the test case? juzhe.zhong@rivai.ai =E6=96=BC 2023=E5=B9=B49=E6=9C= =8820=E6=97=A5 =E9=80=B1=E4=B8=89 08:44 =E5=AF=AB=E9=81=93=EF=BC=9A > I didn't see this issue. > They should be the bogus FAILs. > We should either fix testcases or ignore them. > > ------------------------------ > juzhe.zhong@rivai.ai > > > *From:* Patrick O'Neill > *Date:* 2023-09-20 08:34 > *To:* Juzhe-Zhong ; Robin Dapp ; > gcc-patches > *CC:* kito.cheng ; kito.cheng > ; jeffreyalaw ; Palmer > Dabbelt ; Edwin Lu ; > joern.rennecke ; jeremy.bennett > ; gnu-toolchain > *Subject:* Re: [Committed] RISC-V: Support VLS unary floating-point > patterns > Hi, > > This patch highlights an issue Edwin and I have been having with the > testsuite where rv64 testcases are run when testing rv32gcv. > > There's a large number of new failures in the rv32gcv testsuite from > this seemingly innocuous patch. > > https://github.com/ewlu/riscv-gnu-toolchain/issues/166 > (The repo is still a WIP - eventually will be non-gating patchworks > pre-commit CI) > > From Edwin and my investigation the failures for rv32gcv look like [1]. > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/u= sr/include/gnu/stubs.h:17:11: > > fatal error: gnu/stubs-lp64d.h: No such file or directory > compilation terminated. > > Top of the failing testcase: > /* { dg-do compile } */ > /* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 > -fno-schedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm= 8" } > */ > > #include "def.h" > > The dg-options explicitly set rv64gcv, so I don't think this testcase > should even be executed. > > For the 3 new failures on rv64gcv, they all explicitly set rv32gcv. > /* { dg-options "-march=3Drv32gcv -mabi=3Dilp32d -O3" } */ > > These are seen on non-multilib builds. Multilib rv32/64gc does not > appear to have the same issue when compiling (we're currently testing > multilib rv32/64gcv to see if they encounter issues when executing). > > Are other people seeing similar errors/is this a known issue? > > Patrick > > [1]: > Executing on host: > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc= -linux-stage2/gcc/xgcc > > -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-g= cc-linux-stage2/gcc/ > > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsui= te/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c > > -march=3Drv32gcv -mabi=3Dilp32d -mcmodel=3Dmedlow -fdiagnostics-plain-out= put > -O3 -ftree-vectorize --param riscv-autovec-preference=3Dscalable > -march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-schedule-insns > -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8 -ffat-lto-objects > -fno-ident -S -o floating-point-mul-3.s (timeout =3D 600) > spawn -ignore SIGHUP > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc= -linux-stage2/gcc/xgcc > > -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-g= cc-linux-stage2/gcc/ > > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsui= te/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c > > -march=3Drv32gcv -mabi=3Dilp32d -mcmodel=3Dmedlow -fdiagnostics-plain-out= put > -O3 -ftree-vectorize --param riscv-autovec-preference=3Dscalable > -march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-schedule-insns > -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8 -ffat-lto-objects > -fno-ident -S -o floating-point-mul-3.s > In file included from > > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/u= sr/include/features.h:515, > from > > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/u= sr/include/bits/libc-header-start.h:33, > from > > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/u= sr/include/math.h:27, > from > > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsui= te/gcc.target/riscv/rvv/autovec/vls/def.h:2, > from > > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsui= te/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c:4: > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/u= sr/include/gnu/stubs.h:17:11: > > fatal error: gnu/stubs-lp64d.h: No such file or directory > compilation terminated. > compiler exited with status 1 > FAIL: gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -O3 > -ftree-vectorize --param riscv-autovec-preference=3Dscalable (test for > excess errors) > > On 9/19/23 04:26, Juzhe-Zhong wrote: > > Extend current VLA patterns with VLS modes. > > > > Regression all passed. > > > > gcc/ChangeLog: > > > > * config/riscv/autovec.md: Extend VLS modes. > > * config/riscv/vector.md: Ditto. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test. > > * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test. > > > > --- > > gcc/config/riscv/autovec.md | 12 ++--- > > gcc/config/riscv/vector.md | 20 +++---- > > .../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +- > > .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52 +++++++++++++++++++ > > 4 files changed, 70 insertions(+), 17 deletions(-) > > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > > > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > > index 769ef6daa36..75ed7ae4f2e 100644 > > --- a/gcc/config/riscv/autovec.md > > +++ b/gcc/config/riscv/autovec.md > > @@ -1031,9 +1031,9 @@ > > ;; - vfneg.v/vfabs.v > > ;; > -------------------------------------------------------------------------= ------ > > (define_insn_and_split "2" > > - [(set (match_operand:VF 0 "register_operand") > > - (any_float_unop_nofrm:VF > > - (match_operand:VF 1 "register_operand")))] > > + [(set (match_operand:V_VLSF 0 "register_operand") > > + (any_float_unop_nofrm:V_VLSF > > + (match_operand:V_VLSF 1 "register_operand")))] > > "TARGET_VECTOR && can_create_pseudo_p ()" > > "#" > > "&& 1" > > @@ -1052,9 +1052,9 @@ > > ;; - vfsqrt.v > > ;; > -------------------------------------------------------------------------= ------ > > (define_insn_and_split "2" > > - [(set (match_operand:VF 0 "register_operand") > > - (any_float_unop:VF > > - (match_operand:VF 1 "register_operand")))] > > + [(set (match_operand:V_VLSF 0 "register_operand") > > + (any_float_unop:V_VLSF > > + (match_operand:V_VLSF 1 "register_operand")))] > > "TARGET_VECTOR && can_create_pseudo_p ()" > > "#" > > "&& 1" > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > > index f7f37da692a..f66ffebba24 100644 > > --- a/gcc/config/riscv/vector.md > > +++ b/gcc/config/riscv/vector.md > > @@ -6756,8 +6756,8 @@ > > ;; > -------------------------------------------------------------------------= ------ > > > > (define_insn "@pred_" > > - [(set (match_operand:VF 0 "register_operand" "=3Dvd, vd, v= r, > vr") > > - (if_then_else:VF > > + [(set (match_operand:V_VLSF 0 "register_operand" "=3Dvd, v= d, > vr, vr") > > + (if_then_else:V_VLSF > > (unspec: > > [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") > > (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") > > @@ -6768,9 +6768,9 @@ > > (reg:SI VL_REGNUM) > > (reg:SI VTYPE_REGNUM) > > (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > > - (any_float_unop:VF > > - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > > - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > + (any_float_unop:V_VLSF > > + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, > vr")) > > + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, > 0")))] > > "TARGET_VECTOR" > > "vf.v\t%0,%3%p1" > > [(set_attr "type" "") > > @@ -6783,8 +6783,8 @@ > > (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) > > > > (define_insn "@pred_" > > - [(set (match_operand:VF 0 "register_operand" "=3Dvd, vd, v= r, > vr") > > - (if_then_else:VF > > + [(set (match_operand:V_VLSF 0 "register_operand" "=3Dvd, v= d, > vr, vr") > > + (if_then_else:V_VLSF > > (unspec: > > [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") > > (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") > > @@ -6793,9 +6793,9 @@ > > (match_operand 7 "const_int_operand" " i, i, i, i") > > (reg:SI VL_REGNUM) > > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > > - (any_float_unop_nofrm:VF > > - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > > - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > > + (any_float_unop_nofrm:V_VLSF > > + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, > vr")) > > + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, > 0")))] > > "TARGET_VECTOR" > > "vf.v\t%0,%3%p1" > > [(set_attr "type" "") > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > > index 5df90704885..d7b721b4e3e 100644 > > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > > @@ -1,4 +1,5 @@ > > #include > > +#include > > > > typedef int8_t v1qi __attribute__ ((vector_size (1))); > > typedef int8_t v2qi __attribute__ ((vector_size (2))); > > @@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size > (4096))); > > PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict > b) \ > > > { > \ > > for (int i =3D 0; i < NUM; > ++i) \ > > - a[i] =3D OP > b[i]; \ > > + a[i] =3D OP > (b[i]); \ > > } > > > > #define DEF_CALL_VV(PREFIX, NUM, TYPE, > CALL) \ > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > > new file mode 100644 > > index 00000000000..c2ab0098afa > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > > @@ -0,0 +1,52 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 > -fno-schedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8 > -fdump-tree-optimized" } */ > > + > > +#include "def.h" > > + > > +DEF_OP_V (neg, 2, _Float16, -) > > +DEF_OP_V (neg, 4, _Float16, -) > > +DEF_OP_V (neg, 8, _Float16, -) > > +DEF_OP_V (neg, 16, _Float16, -) > > +DEF_OP_V (neg, 32, _Float16, -) > > +DEF_OP_V (neg, 64, _Float16, -) > > +DEF_OP_V (neg, 128, _Float16, -) > > +DEF_OP_V (neg, 256, _Float16, -) > > +DEF_OP_V (neg, 512, _Float16, -) > > +DEF_OP_V (neg, 1024, _Float16, -) > > +DEF_OP_V (neg, 2048, _Float16, -) > > + > > +DEF_OP_V (neg, 2, float, -) > > +DEF_OP_V (neg, 4, float, -) > > +DEF_OP_V (neg, 8, float, -) > > +DEF_OP_V (neg, 16, float, -) > > +DEF_OP_V (neg, 32, float, -) > > +DEF_OP_V (neg, 64, float, -) > > +DEF_OP_V (neg, 128, float, -) > > +DEF_OP_V (neg, 256, float, -) > > +DEF_OP_V (neg, 512, float, -) > > +DEF_OP_V (neg, 1024, float, -) > > + > > +DEF_OP_V (neg, 2, double, -) > > +DEF_OP_V (neg, 4, double, -) > > +DEF_OP_V (neg, 8, double, -) > > +DEF_OP_V (neg, 16, double, -) > > +DEF_OP_V (neg, 32, double, -) > > +DEF_OP_V (neg, 64, double, -) > > +DEF_OP_V (neg, 128, double, -) > > +DEF_OP_V (neg, 256, double, -) > > +DEF_OP_V (neg, 512, double, -) > > + > > +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 > } } */ > > +/* { dg-final { scan-assembler-not {csrr} } } */ > > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ > > > --00000000000000aae50605bfcbf5--