From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by sourceware.org (Postfix) with ESMTPS id B24BA3858016 for ; Wed, 28 Sep 2022 17:33:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B24BA3858016 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x633.google.com with SMTP id l14so28619866eja.7 for ; Wed, 28 Sep 2022 10:33:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date; bh=unXwFJGyDSmu2boPyinUpzg2ehuFKbzXR7qNK2mBz7E=; b=P/8YUGphq4grw9MRxi5Rp7LoezGvxEiieQ8vajJfAU+90lYTRNbHR+S5OrUbLP6UTa yKbShaXpjMFcxLaEEKY8EQYoG+Sld83o7rtMtt5nXHd6KWwj5lz3z7pX2SrAeojfSpcH PE0ysJPLdZo++LF9hDwrxCQOIRsSyH5ZHqDFurV830FFOTlZ7zbGuFcJ0Lc7iP+h+ivj KNjTtav1Ck12tlyLNX4/R0vHsrNvjIxSbpx0/bHziG6vqUvQFINsiJiZrdPASs8xG7xG 3DPR0Pc1O+teYDfryQjO5qnMN5RdLW0h2kORPnXOOGc9iJ6ShNzeXJppSNZ/VQuoEpcg 34Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date; bh=unXwFJGyDSmu2boPyinUpzg2ehuFKbzXR7qNK2mBz7E=; b=Qp33xq8siGHafpeOW1fkXDpmjgd4mtfteloI0LJbqdXBfO/WtJWHNoSMZaRzSTgKiq xwl3oYLL01Fk0WIKVn2j/vqiD/eCvrIErTSApr/2GLzS7fiF6p8Ud821qN8oyIlsgMIf RI9JUi9mo8Dp5NZr1uAOh9hb1HTlgEmAwuj964QBzAlMzkXuWa7d+zJuylaqFph/PH/Y nf/We0ApxxZt2/R5L6BkeZQ4VTyusfN8g/EufYa0Oa1S+rpv6J1Yr3lk2jIUFIrAhJ1u XWTqko/Army6J9yL+PwKXDPwUrrX3fmf4U8uEv5koWZTcgMJvFVoOqOEAdS5HGaVa7Cl 3IbA== X-Gm-Message-State: ACrzQf3d2BQM+j/o/gy/0KCJHjM/hSgG3qu1SAGkB543rSYnfwvDL34p G9CIRGeyGttIsEgZDbyI4EYCGxhfxeXTGChzcCz9nWMO X-Google-Smtp-Source: AMsMyM6hrfGVrFiAAJQSFk05KPYgCxXjFEhNkuAONRfktv0W84jY72MYkP3UxISvESSPGkK8P8pMeQmhE8nmMEMoL5E= X-Received: by 2002:a17:907:1c20:b0:781:c7fc:518e with SMTP id nc32-20020a1709071c2000b00781c7fc518emr28605688ejc.309.1664386420116; Wed, 28 Sep 2022 10:33:40 -0700 (PDT) MIME-Version: 1.0 References: <20220927092608.228176-1-juzhe.zhong@rivai.ai> In-Reply-To: <20220927092608.228176-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Thu, 29 Sep 2022 01:33:27 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add ABI-defined RVV types. To: juzhe.zhong@rivai.ai Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed with few minor style tweaks :) On Tue, Sep 27, 2022 at 5:27 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config.gcc: Add riscv-vector-builtins.o. > * config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV b= uiltin function. > * config/riscv/riscv-protos.h (riscv_v_ext_enabled_vector_mode_p)= : New function. > * config/riscv/riscv.cc (ENTRY): New macro. > (riscv_v_ext_enabled_vector_mode_p): New function. > (riscv_mangle_type): Add RVV mangle. > (riscv_vector_mode_supported_p): Adjust RVV machine mode. > (riscv_verify_type_context): Add context check for RVV. > (riscv_vector_alignment): Add RVV alignment target hook support. > (TARGET_VECTOR_MODE_SUPPORTED_P): New target hook support. > (TARGET_VERIFY_TYPE_CONTEXT): Ditto. > (TARGET_VECTOR_ALIGNMENT): Ditto. > * config/riscv/t-riscv: Add riscv-vector-builtins.o > * config/riscv/riscv-vector-builtins.cc: New file. > * config/riscv/riscv-vector-builtins.def: New file. > * config/riscv/riscv-vector-builtins.h: New file. > * config/riscv/riscv-vector-switch.def: New file. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/abi-1.c: New test. > * gcc.target/riscv/rvv/base/abi-2.c: New test. > * gcc.target/riscv/rvv/base/abi-3.c: New test. > * gcc.target/riscv/rvv/base/abi-4.c: New test. > * gcc.target/riscv/rvv/base/abi-5.c: New test. > * gcc.target/riscv/rvv/base/abi-6.c: New test. > * gcc.target/riscv/rvv/base/abi-7.c: New test. > * gcc.target/riscv/rvv/rvv.exp: New test. > > --- > gcc/config.gcc | 1 + > gcc/config/riscv/riscv-builtins.cc | 2 + > gcc/config/riscv/riscv-protos.h | 1 + > gcc/config/riscv/riscv-vector-builtins.cc | 281 ++++++++++++++++++ > gcc/config/riscv/riscv-vector-builtins.def | 199 +++++++++++++ > gcc/config/riscv/riscv-vector-builtins.h | 79 +++++ > gcc/config/riscv/riscv-vector-switch.def | 164 ++++++++++ > gcc/config/riscv/riscv.cc | 95 +++++- > gcc/config/riscv/t-riscv | 10 + > .../gcc.target/riscv/rvv/base/abi-1.c | 63 ++++ > .../gcc.target/riscv/rvv/base/abi-2.c | 63 ++++ > .../gcc.target/riscv/rvv/base/abi-3.c | 63 ++++ > .../gcc.target/riscv/rvv/base/abi-4.c | 63 ++++ > .../gcc.target/riscv/rvv/base/abi-5.c | 63 ++++ > .../gcc.target/riscv/rvv/base/abi-6.c | 63 ++++ > .../gcc.target/riscv/rvv/base/abi-7.c | 63 ++++ > gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 47 +++ > 17 files changed, 1319 insertions(+), 1 deletion(-) > create mode 100644 gcc/config/riscv/riscv-vector-builtins.cc > create mode 100644 gcc/config/riscv/riscv-vector-builtins.def > create mode 100644 gcc/config/riscv/riscv-vector-builtins.h > create mode 100644 gcc/config/riscv/riscv-vector-switch.def > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > > diff --git a/gcc/config.gcc b/gcc/config.gcc > index 27ffce3fb50..615a06f87dd 100644 > --- a/gcc/config.gcc > +++ b/gcc/config.gcc > @@ -516,6 +516,7 @@ pru-*-*) > riscv*) > cpu_type=3Driscv > extra_objs=3D"riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten= -memrefs.o riscv-selftests.o" > + extra_objs=3D"${extra_objs} riscv-vector-builtins.o" > d_target_objs=3D"riscv-d.o" > ;; > rs6000*-*-*) > diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-= builtins.cc > index 3009311604d..a51037a8f7a 100644 > --- a/gcc/config/riscv/riscv-builtins.cc > +++ b/gcc/config/riscv/riscv-builtins.cc > @@ -37,6 +37,7 @@ along with GCC; see the file COPYING3. If not see > #include "stringpool.h" > #include "expr.h" > #include "langhooks.h" > +#include "riscv-vector-builtins.h" > > /* Macros to create an enumeration identifier for a function prototype. = */ > #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE > @@ -213,6 +214,7 @@ void > riscv_init_builtins (void) > { > riscv_init_builtin_types (); > + riscv_vector::init_builtins (); > > for (size_t i =3D 0; i < ARRAY_SIZE (riscv_builtins); i++) > { > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-pro= tos.h > index f9a2baa46c7..101361a4b44 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -75,6 +75,7 @@ extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_= insn *); > extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *); > extern bool riscv_gpr_save_operation_p (rtx); > extern void riscv_reinit (void); > +extern bool riscv_v_ext_enabled_vector_mode_p (machine_mode); > > /* Routines implemented in riscv-c.cc. */ > void riscv_cpu_cpp_builtins (cpp_reader *); > diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv= /riscv-vector-builtins.cc > new file mode 100644 > index 00000000000..aca80a11ead > --- /dev/null > +++ b/gcc/config/riscv/riscv-vector-builtins.cc > @@ -0,0 +1,281 @@ > +/* Builtins implementation for RISC-V 'V' Extension for GNU compiler. > + Copyright (C) 2022-2022 Free Software Foundation, Inc. > + Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologie= s Ltd. > + > + This file is part of GCC. > + > + GCC is free software; you can redistribute it and/or modify it > + under the terms of the GNU General Public License as published by > + the Free Software Foundation; either version 3, or (at your option) > + any later version. > + > + GCC is distributed in the hope that it will be useful, but > + WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + General Public License for more details. > + > + You should have received a copy of the GNU General Public License > + along with GCC; see the file COPYING3. If not see > + . */ > + > +#define IN_TARGET_CODE 1 > + > +#include "config.h" > +#include "system.h" > +#include "coretypes.h" > +#include "tm.h" > +#include "tree.h" > +#include "rtl.h" > +#include "tm_p.h" > +#include "memmodel.h" > +#include "insn-codes.h" > +#include "optabs.h" > +#include "recog.h" > +#include "diagnostic.h" > +#include "expr.h" > +#include "function.h" > +#include "fold-const.h" > +#include "gimplify.h" > +#include "explow.h" > +#include "stor-layout.h" > +#include "alias.h" > +#include "langhooks.h" > +#include "stringpool.h" > +#include "attribs.h" > +#include "targhooks.h" > +#include "regs.h" > +#include "riscv-vector-builtins.h" > + > +namespace riscv_vector { > + > +/* Information about each RVV type. */ > +static CONSTEXPR const vector_type_info vector_types[] =3D { > +#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, ARGS...) \ > + {#USER_NAME, #ABI_NAME, "u" #NCHARS #ABI_NAME}, > +#include "riscv-vector-builtins.def" > +}; > + > +/* The scalar type associated with each vector type. */ > +static GTY (()) tree scalar_types[NUM_VECTOR_TYPES]; > +/* The machine mode associated with each vector type. */ > +static GTY (()) machine_mode vector_modes[NUM_VECTOR_TYPES]; > +/* The RVV types, with their built-in > + "__rvv..._t" name. Allow an index of NUM_VECTOR_TYPES, which always > + yields a null tree. */ > +static GTY(()) tree abi_vector_types[NUM_VECTOR_TYPES + 1]; > + > +rvv_switcher::rvv_switcher () > +{ > + /* Set have_regs_of_mode before targetm.init_builtins (). */ > + memcpy (m_old_have_regs_of_mode, have_regs_of_mode, > + sizeof (have_regs_of_mode)); > + for (int i =3D 0; i < NUM_MACHINE_MODES; ++i) > + if (riscv_v_ext_enabled_vector_mode_p ((machine_mode) i)) > + have_regs_of_mode[i] =3D true; > +} > + > +rvv_switcher::~rvv_switcher () > +{ > + /* Recover back have_regs_of_mode. */ > + memcpy (have_regs_of_mode, m_old_have_regs_of_mode, > + sizeof (have_regs_of_mode)); > +} > + > +/* Add type attributes to builtin type tree, currently only the mangled = name. */ > +static void > +add_vector_type_attribute (tree type, const char *mangled_name) > +{ > + tree mangled_name_tree =3D get_identifier (mangled_name); > + tree value =3D tree_cons (NULL_TREE, mangled_name_tree, NULL_TREE); > + TYPE_ATTRIBUTES (type) =3D tree_cons (get_identifier ("RVV type"), val= ue, > + TYPE_ATTRIBUTES (type)); > +} > + > +/* Force TYPE to be a sizeless type. */ > +static void > +make_type_sizeless (tree type) > +{ > + TYPE_ATTRIBUTES (type) =3D tree_cons (get_identifier ("RVV sizeless ty= pe"), > + NULL_TREE, TYPE_ATTRIBUTES (type)); > +} > + > +/* Return true if TYPE is a sizeless type. */ > +static bool > +sizeless_type_p (const_tree type) > +{ > + if (type =3D=3D error_mark_node) > + return NULL_TREE; > + return lookup_attribute ("RVV sizeless type", TYPE_ATTRIBUTES (type)); > +} > + > +/* If TYPE is an ABI-defined RVV type, return its attribute descriptor, > + otherwise return null. */ > +static tree > +lookup_vector_type_attribute (const_tree type) > +{ > + if (type =3D=3D error_mark_node) > + return NULL_TREE; > + return lookup_attribute ("RVV type", TYPE_ATTRIBUTES (type)); > +} > + > +/* If TYPE is a built-in type defined by the RVV ABI, return the mangled= name, > + otherwise return NULL. */ > +const char * > +mangle_builtin_type (const_tree type) > +{ > + if (TYPE_NAME (type) && TREE_CODE (TYPE_NAME (type)) =3D=3D TYPE_DECL) > + type =3D TREE_TYPE (TYPE_NAME (type)); > + if (tree attr =3D lookup_vector_type_attribute (type)) > + if (tree id =3D TREE_VALUE (chain_index (0, TREE_VALUE (attr)))) > + return IDENTIFIER_POINTER (id); > + return NULL; > +} > + > +/* Register the built-in RVV ABI types, such as __rvv_int32m1_t. */ > +static void > +register_builtin_types () > +{ > + /* int32_t/uint32_t defined as `long`/`unsigned long` in RV32, > + but intSI_type_node/unsigned_intSI_type_node is > + `int` and `unsigned int`, so use long_integer_type_node and > + long_unsigned_type_node here for type consistent. */ > + tree int32_type_node > + =3D TARGET_64BIT ? intSI_type_node : long_integer_type_node; > + tree unsigned_int32_type_node > + =3D TARGET_64BIT ? unsigned_intSI_type_node : long_unsigned_type_nod= e; > + > + machine_mode mode; > +#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MO= DE, \ > + VECTOR_MODE_MIN_VLEN_32) = \ > + mode =3D TARGET_MIN_VLEN > 32 ? VECTOR_MODE##mode = \ > + : VECTOR_MODE_MIN_VLEN_32##mode; = \ > + scalar_types[VECTOR_TYPE_##USER_NAME] = \ > + =3D riscv_v_ext_enabled_vector_mode_p (mode) ? SCALAR_TYPE##_type_no= de \ > + : NULL_TREE; = \ > + vector_modes[VECTOR_TYPE_##USER_NAME] = \ > + =3D riscv_v_ext_enabled_vector_mode_p (mode) ? mode : VOIDmode; > +#include "riscv-vector-builtins.def" > + > + for (unsigned int i =3D 0; i < NUM_VECTOR_TYPES; ++i) > + { > + tree eltype =3D scalar_types[i]; > + mode =3D vector_modes[i]; > + /* We disabled the datatypes according '-march'. */ > + if (!eltype) > + continue; > + > + tree vectype =3D build_vector_type_for_mode (eltype, mode); > + gcc_assert ( > + VECTOR_MODE_P (TYPE_MODE (vectype)) && TYPE_MODE (vectype) =3D=3D= mode > + && TYPE_MODE_RAW (vectype) =3D=3D mode && TYPE_ALIGN (vectype) <= =3D 128 > + && known_eq (tree_to_poly_uint64 (TYPE_SIZE (vectype)), > + GET_MODE_BITSIZE (mode))); > + vectype =3D build_distinct_type_copy (vectype); > + gcc_assert (vectype =3D=3D TYPE_MAIN_VARIANT (vectype)); > + SET_TYPE_STRUCTURAL_EQUALITY (vectype); > + TYPE_ARTIFICIAL (vectype) =3D 1; > + TYPE_INDIVISIBLE_P (vectype) =3D 1; > + add_vector_type_attribute (vectype, vector_types[i].mangled_name); > + make_type_sizeless (vectype); > + abi_vector_types[i] =3D vectype; > + lang_hooks.types.register_builtin_type (vectype, > + vector_types[i].abi_name); > + } > +} > + > +/* Initialize all compiler built-ins related to RVV that should be > + defined at start-up. */ > +void > +init_builtins () > +{ > + rvv_switcher rvv; > + if (!TARGET_VECTOR) > + return; > + register_builtin_types (); > +} > + > +/* Implement TARGET_VERIFY_TYPE_CONTEXT for RVV types. */ > +bool > +verify_type_context (location_t loc, type_context_kind context, const_tr= ee type, > + bool silent_p) > +{ > + if (!sizeless_type_p (type)) > + return true; > + > + switch (context) > + { > + case TCTX_SIZEOF: > + case TCTX_STATIC_STORAGE: > + if (!silent_p) > + error_at (loc, "RVV type %qT does not have a fixed size", type); > + > + return false; > + > + case TCTX_ALIGNOF: > + if (!silent_p) > + error_at (loc, "RVV type %qT does not have a defined alignment", = type); > + > + return false; > + > + case TCTX_THREAD_STORAGE: > + if (!silent_p) > + error_at (loc, > + "variables of type %qT cannot have thread-local" > + " storage duration", > + type); > + > + return false; > + > + case TCTX_POINTER_ARITH: > + if (!silent_p) > + error_at (loc, "arithmetic on pointer to RVV type %qT", type); > + > + return false; > + > + case TCTX_FIELD: > + if (silent_p) > + ; > + else if (lang_GNU_CXX ()) > + error_at (loc, "member variables cannot have RVV type %qT", type)= ; > + else > + error_at (loc, "fields cannot have RVV type %qT", type); > + > + return false; > + > + case TCTX_ARRAY_ELEMENT: > + if (!silent_p) > + error_at (loc, "array elements cannot have RVV type %qT", type); > + > + return false; > + > + case TCTX_ALLOCATION: > + if (!silent_p) > + error_at (loc, "cannot allocate objects with RVV type %qT", type)= ; > + > + return false; > + > + case TCTX_DEALLOCATION: > + if (!silent_p) > + error_at (loc, "cannot delete objects with RVV type %qT", type); > + > + return false; > + > + case TCTX_EXCEPTIONS: > + if (!silent_p) > + error_at (loc, "cannot throw or catch RVV type %qT", type); > + > + return false; > + > + case TCTX_CAPTURE_BY_COPY: > + if (!silent_p) > + error_at (loc, "capture by copy of RVV type %qT", type); > + > + return false; > + } > + > + gcc_unreachable (); > +} > + > +} // end namespace riscv_vector > + > +using namespace riscv_vector; > \ No newline at end of file > diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/risc= v/riscv-vector-builtins.def > new file mode 100644 > index 00000000000..5f154078fbb > --- /dev/null > +++ b/gcc/config/riscv/riscv-vector-builtins.def > @@ -0,0 +1,199 @@ > +/* Builtins macros for RISC-V 'V' Extension for GNU compiler. > + Copyright (C) 2022-2022 Free Software Foundation, Inc. > + Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologie= s Ltd. > + > +This file is part of GCC. > + > +GCC is free software; you can redistribute it and/or modify > +it under the terms of the GNU General Public License as published by > +the Free Software Foundation; either version 3, or (at your option) > +any later version. > + > +GCC is distributed in the hope that it will be useful, > +but WITHOUT ANY WARRANTY; without even the implied warranty of > +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +GNU General Public License for more details. > + > +You should have received a copy of the GNU General Public License > +along with GCC; see the file COPYING3. If not see > +. */ > + > +/* Use "DEF_RVV_TYPE" macro to define RVV datatype builtins. > + 1.The 1 argument is the name exposed to users. > + For example, "vint32m1_t". > + 2.The 2 argument is the length of ABI-name. > + For example, length of "__rvv_int32m1_t" is 15. > + 3.The 3 argument is the ABI-name. For example, "__rvv_int32m1_t". > + 4.The 4 argument is associated scalar type which is used in > + "build_vector_type_for_mode". For "vint32m1_t", we use "intSI_type_= node" in > + RV64. Otherwise, we use "long_integer_type_node". > + 5.The 5 and 6 argument are the machine modes of corresponding RVV typ= e used > + in "build_vector_type_for_mode". For "vint32m1_t", we use VNx2SImod= e when > + TARGET_MIN_VLEN > 32. Otherwise the machine mode is VNx1SImode. */ > + > +#ifndef DEF_RVV_TYPE > +#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MO= DE, \ > + VECTOR_MODE_MIN_VLEN_32) > +#endif > + > +/* SEW/LMUL =3D 64: > + Only enable when TARGET_MIN_VLEN > 32 and machine mode =3D VNx1BImode= . */ > +DEF_RVV_TYPE (vbool64_t, 14, __rvv_bool64_t, boolean, VNx1BI, VOID) > +/* SEW/LMUL =3D 32: > + Machine mode =3D VNx2BImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx1BImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vbool32_t, 14, __rvv_bool32_t, boolean, VNx2BI, VNx1BI) > +/* SEW/LMUL =3D 16: > + Machine mode =3D VNx2BImode when TARGET_MIN_VLEN =3D 32. > + Machine mode =3D VNx4BImode when TARGET_MIN_VLEN > 32. */ > +DEF_RVV_TYPE (vbool16_t, 14, __rvv_bool16_t, boolean, VNx4BI, VNx2BI) > +/* SEW/LMUL =3D 8: > + Machine mode =3D VNx8BImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx4BImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vbool8_t, 13, __rvv_bool8_t, boolean, VNx8BI, VNx4BI) > +/* SEW/LMUL =3D 4: > + Machine mode =3D VNx16BImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx8BImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vbool4_t, 13, __rvv_bool4_t, boolean, VNx16BI, VNx8BI) > +/* SEW/LMUL =3D 2: > + Machine mode =3D VNx32BImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx16BImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vbool2_t, 13, __rvv_bool2_t, boolean, VNx32BI, VNx16BI) > +/* SEW/LMUL =3D 1: > + Machine mode =3D VNx64BImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx32BImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vbool1_t, 13, __rvv_bool1_t, boolean, VNx64BI, VNx32BI) > + > +/* LMUL =3D 1/8: > + Only enble when TARGET_MIN_VLEN > 32 and machine mode =3D VNx1QImode.= */ > +DEF_RVV_TYPE (vint8mf8_t, 15, __rvv_int8mf8_t, intQI, VNx1QI, VOID) > +DEF_RVV_TYPE (vuint8mf8_t, 16, __rvv_uint8mf8_t, unsigned_intQI, VNx1QI,= VOID) > +/* LMUL =3D 1/4: > + Machine mode =3D VNx2QImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx1QImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint8mf4_t, 15, __rvv_int8mf4_t, intQI, VNx2QI, VNx1QI) > +DEF_RVV_TYPE (vuint8mf4_t, 16, __rvv_uint8mf4_t, unsigned_intQI, VNx2QI,= VNx1QI) > +/* LMUL =3D 1/2: > + Machine mode =3D VNx4QImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx2QImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint8mf2_t, 15, __rvv_int8mf2_t, intQI, VNx4QI, VNx2QI) > +DEF_RVV_TYPE (vuint8mf2_t, 16, __rvv_uint8mf2_t, unsigned_intQI, VNx4QI,= VNx2QI) > +/* LMUL =3D 1: > + Machine mode =3D VNx8QImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx4QImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint8m1_t, 14, __rvv_int8m1_t, intQI, VNx8QI, VNx4QI) > +DEF_RVV_TYPE (vuint8m1_t, 15, __rvv_uint8m1_t, unsigned_intQI, VNx8QI, V= Nx4QI) > +/* LMUL =3D 2: > + Machine mode =3D VNx16QImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx8QImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint8m2_t, 14, __rvv_int8m2_t, intQI, VNx16QI, VNx8QI) > +DEF_RVV_TYPE (vuint8m2_t, 15, __rvv_uint8m2_t, unsigned_intQI, VNx16QI, = VNx8QI) > +/* LMUL =3D 4: > + Machine mode =3D VNx32QImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx16QImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint8m4_t, 14, __rvv_int8m4_t, intQI, VNx32QI, VNx16QI) > +DEF_RVV_TYPE (vuint8m4_t, 15, __rvv_uint8m4_t, unsigned_intQI, VNx32QI, = VNx16QI) > +/* LMUL =3D 8: > + Machine mode =3D VNx64QImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx32QImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint8m8_t, 14, __rvv_int8m8_t, intQI, VNx64QI, VNx32QI) > +DEF_RVV_TYPE (vuint8m8_t, 15, __rvv_uint8m8_t, unsigned_intQI, VNx64QI, = VNx32QI) > + > +/* LMUL =3D 1/4: > + Only enble when TARGET_MIN_VLEN > 32 and machine mode =3D VNx1HImode.= */ > +DEF_RVV_TYPE (vint16mf4_t, 16, __rvv_int16mf4_t, intHI, VNx1HI, VOID) > +DEF_RVV_TYPE (vuint16mf4_t, 17, __rvv_uint16mf4_t, unsigned_intHI, VNx1H= I, VOID) > +/* LMUL =3D 1/2: > + Machine mode =3D VNx2HImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx1HImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint16mf2_t, 16, __rvv_int16mf2_t, intHI, VNx2HI, VNx1HI) > +DEF_RVV_TYPE (vuint16mf2_t, 17, __rvv_uint16mf2_t, unsigned_intHI, VNx2H= I, > + VNx1HI) > +/* LMUL =3D 1: > + Machine mode =3D VNx4HImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx2HImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint16m1_t, 15, __rvv_int16m1_t, intHI, VNx4HI, VNx2HI) > +DEF_RVV_TYPE (vuint16m1_t, 16, __rvv_uint16m1_t, unsigned_intHI, VNx4HI,= VNx2HI) > +/* LMUL =3D 2: > + Machine mode =3D VNx8HImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx4HImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint16m2_t, 15, __rvv_int16m2_t, intHI, VNx8HI, VNx4HI) > +DEF_RVV_TYPE (vuint16m2_t, 16, __rvv_uint16m2_t, unsigned_intHI, VNx8HI,= VNx4HI) > +/* LMUL =3D 4: > + Machine mode =3D VNx16HImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx8HImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint16m4_t, 15, __rvv_int16m4_t, intHI, VNx16HI, VNx8HI) > +DEF_RVV_TYPE (vuint16m4_t, 16, __rvv_uint16m4_t, unsigned_intHI, VNx16HI= , > + VNx8HI) > +/* LMUL =3D 8: > + Machine mode =3D VNx32HImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx16HImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint16m8_t, 15, __rvv_int16m8_t, intHI, VNx32HI, VNx16HI) > +DEF_RVV_TYPE (vuint16m8_t, 16, __rvv_uint16m8_t, unsigned_intHI, VNx32HI= , > + VNx16HI) > + > +/* LMUL =3D 1/2: > + Only enble when TARGET_MIN_VLEN > 32 and machine mode =3D VNx1SImode.= */ > +DEF_RVV_TYPE (vint32mf2_t, 16, __rvv_int32mf2_t, int32, VNx1SI, VOID) > +DEF_RVV_TYPE (vuint32mf2_t, 17, __rvv_uint32mf2_t, unsigned_int32, VNx1S= I, VOID) > +/* LMUL =3D 1: > + Machine mode =3D VNx2SImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx1SImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint32m1_t, 15, __rvv_int32m1_t, int32, VNx2SI, VNx1SI) > +DEF_RVV_TYPE (vuint32m1_t, 16, __rvv_uint32m1_t, unsigned_int32, VNx2SI,= VNx1SI) > +/* LMUL =3D 2: > + Machine mode =3D VNx4SImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx2SImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint32m2_t, 15, __rvv_int32m2_t, int32, VNx4SI, VNx2SI) > +DEF_RVV_TYPE (vuint32m2_t, 16, __rvv_uint32m2_t, unsigned_int32, VNx4SI,= VNx2SI) > +/* LMUL =3D 4: > + Machine mode =3D VNx8SImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx4SImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint32m4_t, 15, __rvv_int32m4_t, int32, VNx8SI, VNx4SI) > +DEF_RVV_TYPE (vuint32m4_t, 16, __rvv_uint32m4_t, unsigned_int32, VNx8SI,= VNx4SI) > +/* LMUL =3D 8: > + Machine mode =3D VNx16SImode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx8SImode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vint32m8_t, 15, __rvv_int32m8_t, int32, VNx16SI, VNx8SI) > +DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, unsigned_int32, VNx16SI= , > + VNx8SI) > + > +/* SEW =3D 64: > + Disable when TARGET_MIN_VLEN > 32. */ > +DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, intDI, VNx1DI, VOID) > +DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, unsigned_intDI, VNx1DI,= VOID) > +DEF_RVV_TYPE (vint64m2_t, 15, __rvv_int64m2_t, intDI, VNx2DI, VOID) > +DEF_RVV_TYPE (vuint64m2_t, 16, __rvv_uint64m2_t, unsigned_intDI, VNx2DI,= VOID) > +DEF_RVV_TYPE (vint64m4_t, 15, __rvv_int64m4_t, intDI, VNx4DI, VOID) > +DEF_RVV_TYPE (vuint64m4_t, 16, __rvv_uint64m4_t, unsigned_intDI, VNx4DI,= VOID) > +DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, intDI, VNx8DI, VOID) > +DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, unsigned_intDI, VNx8DI,= VOID) > + > +/* LMUL =3D 1/2: > + Only enble when TARGET_MIN_VLEN > 32 and machine mode =3D VNx1SFmode.= */ > +DEF_RVV_TYPE (vfloat32mf2_t, 18, __rvv_float32mf2_t, float, VNx1SF, VOID= ) > +/* LMUL =3D 1: > + Machine mode =3D VNx2SFmode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx1SFmode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vfloat32m1_t, 17, __rvv_float32m1_t, float, VNx2SF, VNx1SF= ) > +/* LMUL =3D 2: > + Machine mode =3D VNx4SFmode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx2SFmode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vfloat32m2_t, 17, __rvv_float32m2_t, float, VNx4SF, VNx2SF= ) > +/* LMUL =3D 4: > + Machine mode =3D VNx8SFmode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx4SFmode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vfloat32m4_t, 17, __rvv_float32m4_t, float, VNx8SF, VNx4SF= ) > +/* LMUL =3D 8: > + Machine mode =3D VNx16SFmode when TARGET_MIN_VLEN > 32. > + Machine mode =3D VNx8SFmode when TARGET_MIN_VLEN =3D 32. */ > +DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8S= F) > + > +/* SEW =3D 64: > + Disable when TARGET_VECTOR_FP64. */ > +DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID) > +DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID) > +DEF_RVV_TYPE (vfloat64m4_t, 17, __rvv_float64m4_t, double, VNx4DF, VOID) > +DEF_RVV_TYPE (vfloat64m8_t, 17, __rvv_float64m8_t, double, VNx8DF, VOID) > + > +#undef DEF_RVV_TYPE > \ No newline at end of file > diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/= riscv-vector-builtins.h > new file mode 100644 > index 00000000000..2806f0852be > --- /dev/null > +++ b/gcc/config/riscv/riscv-vector-builtins.h > @@ -0,0 +1,79 @@ > +/* Builtins definitions for RISC-V 'V' Extension for GNU compiler. > + Copyright (C) 2022-2022 Free Software Foundation, Inc. > + Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologie= s Ltd. > + > + This file is part of GCC. > + > + GCC is free software; you can redistribute it and/or modify it > + under the terms of the GNU General Public License as published by > + the Free Software Foundation; either version 3, or (at your option) > + any later version. > + > + GCC is distributed in the hope that it will be useful, but > + WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + General Public License for more details. > + > + You should have received a copy of the GNU General Public License > + along with GCC; see the file COPYING3. If not see > + . */ > + > +#ifndef GCC_RISCV_V_BUILTINS_H > +#define GCC_RISCV_V_BUILTINS_H > + > +namespace riscv_vector { > + > +/* Static information about each vector type. */ > +struct vector_type_info > +{ > + /* The name of the type as declared by riscv_vector.h > + which is recommend to use. For example: 'vint32m1_t'. */ > + const char *user_name; > + > + /* ABI name of vector type. The type is always available > + under this name, even when riscv_vector.h isn't included. > + For example: '__rvv_int32m1_t'. */ > + const char *abi_name; > + > + /* The C++ mangling of ABI_NAME. */ > + const char *mangled_name; > +}; > + > +/* Enumerates the RVV types, together called > + "vector types" for brevity. */ > +enum vector_type_index > +{ > +#define DEF_RVV_TYPE(USER_NAME, ABI_NAME, NCHARS, ARGS...) \ > + VECTOR_TYPE_##USER_NAME, > +#include "riscv-vector-builtins.def" > + NUM_VECTOR_TYPES > +}; > + > +/* RAII class for enabling enough RVV features to define the built-in > + types and implement the riscv_vector.h pragma. > + > + Note: According to 'TYPE_MODE' macro implementation, we need set > + have_regs_of_mode[mode] to be true if we want to get the exact mode > + from 'TYPE_MODE'. However, have_regs_of_mode has not been set yet in > + targetm.init_builtins (). We need rvv_switcher to set have_regs_of_mo= de > + before targetm.init_builtins () and recover back have_regs_of_mode > + after targetm.init_builtins (). */ > +class rvv_switcher > +{ > +public: > + rvv_switcher (); > + ~rvv_switcher (); > + > +private: > + bool m_old_have_regs_of_mode[MAX_MACHINE_MODE]; > +}; > + > +void init_builtins (); > +const char *mangle_builtin_type (const_tree); > +#ifdef GCC_TARGET_H > +bool verify_type_context (location_t, type_context_kind, const_tree, boo= l); > +#endif > + > +} // end namespace riscv_vector > + > +#endif > \ No newline at end of file > diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/= riscv-vector-switch.def > new file mode 100644 > index 00000000000..e519f743064 > --- /dev/null > +++ b/gcc/config/riscv/riscv-vector-switch.def > @@ -0,0 +1,164 @@ > +/* Machine mode switch for RISC-V 'V' Extension for GNU compiler. > + Copyright (C) 2022-2022 Free Software Foundation, Inc. > + Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologie= s Ltd. > + > +This file is part of GCC. > + > +GCC is free software; you can redistribute it and/or modify > +it under the terms of the GNU General Public License as published by > +the Free Software Foundation; either version 3, or (at your option) > +any later version. > + > +GCC is distributed in the hope that it will be useful, > +but WITHOUT ANY WARRANTY; without even the implied warranty of > +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +GNU General Public License for more details. > + > +You should have received a copy of the GNU General Public License > +along with GCC; see the file COPYING3. If not see > +. */ > + > +/* This file is enable or disable the RVV modes according '-march'. */ > + > +/* According to rvv-intrinsic and RISC-V 'V' Extension ISA document: > + https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-in= trinsic-rfc.md. > + https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc. > + > + Data Types > + Encode SEW and LMUL into data types. > + We enforce the constraint LMUL =E2=89=A5 SEW/ELEN in the implementati= on. > + There are the following data types for MIN_VLEN > 32. > + > +Note: N/A means the corresponding vector type is disabled. > + > +|Types |LMUL=3D1|LMUL=3D2 |LMUL=3D4 |LMUL=3D8 |LMUL=3D1/2|LMUL=3D1/4|L= MUL=3D1/8| > +|int64_t |VNx1DI|VNx2DI |VNx4DI |VNx8DI |N/A |N/A |N/A | > +|uint64_t|VNx1DI|VNx2DI |VNx4DI |VNx8DI |N/A |N/A |N/A | > +|int32_t |VNx2SI|VNx4SI |VNx8SI |VNx16SI|VNx1SI |N/A |N/A | > +|uint32_t|VNx2SI|VNx4SI |VNx8SI |VNx16SI|VNx1SI |N/A |N/A | > +|int16_t |VNx4HI|VNx8HI |VNx16HI|VNx32HI|VNx2HI |VNx1HI |N/A | > +|uint16_t|VNx4HI|VNx8HI |VNx16HI|VNx32HI|VNx2HI |VNx1HI |N/A | > +|int8_t |VNx8QI|VNx16QI|VNx32QI|VNx64QI|VNx4QI |VNx2QI |VNx1QI | > +|uint8_t |VNx8QI|VNx16QI|VNx32QI|VNx64QI|VNx4QI |VNx2QI |VNx1QI | > +|float64 |VNx1DF|VNx2DF |VNx4DF |VNx8DF |N/A |N/A |N/A | > +|float32 |VNx2SF|VNx4SF |VNx8SF |VNx16SF|VNx1SF |N/A |N/A | > +|float16 |VNx4HF|VNx8HF |VNx16HF|VNx32HF|VNx2HF |VNx1HF |N/A | > + > +Mask Types Encode the ratio of SEW/LMUL into the > +mask types. There are the following mask types. > + > +n =3D SEW/LMUL > + > +|Types|n=3D1 |n=3D2 |n=3D4 |n=3D8 |n=3D16 |n=3D32 |n=3D64 = | > +|bool |VNx64BI|VNx32BI|VNx16BI|VNx8BI|VNx4BI|VNx2BI|VNx1BI| > + > +There are the following data types for MIN_VLEN =3D 32. > + > +|Types |LMUL=3D1|LMUL=3D2|LMUL=3D4 |LMUL=3D8 |LMUL=3D1/2|LMUL=3D1/4|LM= UL=3D1/8| > +|int64_t |N/A |N/A |N/A |N/A |N/A |N/A |N/A | > +|uint64_t|N/A |N/A |N/A |N/A |N/A |N/A |N/A | > +|int32_t |VNx1SI|VNx2SI|VNx4SI |VNx8SI |N/A |N/A |N/A | > +|uint32_t|VNx1SI|VNx2SI|VNx4SI |VNx8SI |N/A |N/A |N/A | > +|int16_t |VNx2HI|VNx4HI|VNx8HI |VNx16HI|VNx1HI |N/A |N/A | > +|uint16_t|VNx2HI|VNx4HI|VNx8HI |VNx16HI|VNx1HI |N/A |N/A | > +|int8_t |VNx4QI|VNx8QI|VNx16QI|VNx32QI|VNx2QI |VNx1QI |N/A | > +|uint8_t |VNx4QI|VNx8QI|VNx16QI|VNx32QI|VNx2QI |VNx1QI |N/A | > +|float64 |N/A |N/A |N/A |N/A |N/A |N/A |N/A | > +|float32 |VNx1SF|VNx2SF|VNx4SF |VNx8SF |N/A |N/A |N/A | > +|float16 |VNx2HF|VNx4HF|VNx8HF |VNx16HF|VNx1HF |N/A |N/A | > + > +Mask Types Encode the ratio of SEW/LMUL into the > +mask types. There are the following mask types. > + > +n =3D SEW/LMUL > + > +|Types|n=3D1 |n=3D2 |n=3D4 |n=3D8 |n=3D16 |n=3D32 |n=3D64| > +|bool |VNx32BI|VNx16BI|VNx8BI|VNx4BI|VNx2BI|VNx1BI|N/A | > + > +TODO: FP16 vector needs support of 'zvfh', we don't support it yet. */ > + > +/* Return 'REQUIREMENT' for machine_mode 'MODE'. > + For example: 'MODE' =3D VNx64BImode needs TARGET_MIN_VLEN > 32. */ > +#ifndef ENTRY > +#define ENTRY(MODE, REQUIREMENT) > +#endif > +/* Flag of FP32 vector. */ > +#ifndef TARGET_VECTOR_FP32 > +#define TARGET_VECTOR_FP32 = \ > + (TARGET_HARD_FLOAT && (TARGET_VECTOR_ELEN_FP_32 || TARGET_VECTOR_ELEN_= FP_64)) > +#endif > +/* Flag of FP64 vector. */ > +#ifndef TARGET_VECTOR_FP64 > +#define TARGET_VECTOR_FP64 = \ > + (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64 && (TARGET_MIN_VLEN >= 32)) > +#endif > + > +/* Mask modes. Disable VNx64BImode when TARGET_MIN_VLEN =3D=3D 32. */ > +ENTRY (VNx64BI, TARGET_MIN_VLEN > 32) > +ENTRY (VNx32BI, true) > +ENTRY (VNx16BI, true) > +ENTRY (VNx8BI, true) > +ENTRY (VNx4BI, true) > +ENTRY (VNx2BI, true) > +ENTRY (VNx1BI, true) > + > +/* SEW =3D 8. Disable VNx64QImode when TARGET_MIN_VLEN =3D=3D 32. */ > +ENTRY (VNx64QI, TARGET_MIN_VLEN > 32) > +ENTRY (VNx32QI, true) > +ENTRY (VNx16QI, true) > +ENTRY (VNx8QI, true) > +ENTRY (VNx4QI, true) > +ENTRY (VNx2QI, true) > +ENTRY (VNx1QI, true) > + > +/* SEW =3D 16. Disable VNx32HImode when TARGET_MIN_VLEN =3D=3D 32. */ > +ENTRY (VNx32HI, TARGET_MIN_VLEN > 32) > +ENTRY (VNx16HI, true) > +ENTRY (VNx8HI, true) > +ENTRY (VNx4HI, true) > +ENTRY (VNx2HI, true) > +ENTRY (VNx1HI, true) > + > +/* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported. = */ > +ENTRY (VNx32HF, false) > +ENTRY (VNx16HF, false) > +ENTRY (VNx8HF, false) > +ENTRY (VNx4HF, false) > +ENTRY (VNx2HF, false) > +ENTRY (VNx1HF, false) > + > +/* SEW =3D 32. Disable VNx16SImode when TARGET_MIN_VLEN =3D=3D 32. > + For single-precision floating-point, we need TARGET_VECTOR_FP32 =3D= =3D > + RVV_ENABLE. */ > +ENTRY (VNx16SI, TARGET_MIN_VLEN > 32) > +ENTRY (VNx8SI, true) > +ENTRY (VNx4SI, true) > +ENTRY (VNx2SI, true) > +ENTRY (VNx1SI, true) > + > +ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32)) > +ENTRY (VNx8SF, TARGET_VECTOR_FP32) > +ENTRY (VNx4SF, TARGET_VECTOR_FP32) > +ENTRY (VNx2SF, TARGET_VECTOR_FP32) > +ENTRY (VNx1SF, TARGET_VECTOR_FP32) > + > +/* SEW =3D 64. Enable when TARGET_MIN_VLEN > 32. > + For double-precision floating-point, we need TARGET_VECTOR_FP64 =3D= =3D > + RVV_ENABLE. */ > +ENTRY (VNx8DI, TARGET_MIN_VLEN > 32) > +ENTRY (VNx4DI, TARGET_MIN_VLEN > 32) > +ENTRY (VNx2DI, TARGET_MIN_VLEN > 32) > +ENTRY (VNx1DI, TARGET_MIN_VLEN > 32) > + > +ENTRY (VNx8DF, TARGET_VECTOR_FP64 && (TARGET_MIN_VLEN > 32)) > +ENTRY (VNx4DF, TARGET_VECTOR_FP64) > +ENTRY (VNx2DF, TARGET_VECTOR_FP64) > +ENTRY (VNx1DF, TARGET_VECTOR_FP64) > + > +/* SEW =3D 128. Disable all of them. */ > +ENTRY (VNx2TI, false) > +ENTRY (VNx2TF, false) > + > +#undef TARGET_VECTOR_FP32 > +#undef TARGET_VECTOR_FP64 > +#undef ENTRY > \ No newline at end of file > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 4d5d88798ea..01298d2fc0d 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -59,6 +59,7 @@ along with GCC; see the file COPYING3. If not see > #include "opts.h" > #include "tm-constrs.h" > #include "rtl-iter.h" > +#include "riscv-vector-builtins.h" > > /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ > #define UNSPEC_ADDRESS_P(X) \ > @@ -375,6 +376,11 @@ static const struct attribute_spec riscv_attribute_t= able[] =3D > { "interrupt", 0, 1, false, true, true, false, > riscv_handle_type_attribute, NULL }, > > + /* The following two are used for the built-in properties of the Vecto= r type > + and are not used externally */ > + {"RVV sizeless type", 4, 4, false, true, false, true, NULL, NULL}, > + {"RVV type", 0, 0, false, true, false, true, NULL, NULL}, > + > /* The last attribute spec is set to be NULL. */ > { NULL, 0, 0, false, false, false, false, NULL, NULL } > }; > @@ -942,7 +948,37 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_typ= e, machine_mode mode, > static bool > riscv_v_ext_vector_mode_p (machine_mode mode) > { > - return VECTOR_MODE_P (mode); > +#define ENTRY(MODE, REQUIREMENT) = \ > + case MODE##mode: = \ > + return true; > + switch (mode) > + { > +#include "riscv-vector-switch.def" > + default: > + return false; > + } > + > + return false; > +} > + > +/* Return true if mode is the RVV enabled mode. > + For example: 'VNx1DI' mode is disabled if MIN_VLEN =3D=3D 32. > + 'VNx1SI' mode is enabled if MIN_VLEN =3D=3D 32. */ > + > +bool > +riscv_v_ext_enabled_vector_mode_p (machine_mode mode) > +{ > +#define ENTRY(MODE, REQUIREMENT) = \ > + case MODE##mode: = \ > + return REQUIREMENT; > + switch (mode) > + { > +#include "riscv-vector-switch.def" > + default: > + return false; > + } > + > + return false; > } > > /* Return true if X is a valid address for machine mode MODE. If it is, > @@ -6180,6 +6216,16 @@ riscv_mangle_type (const_tree type) > if (TREE_CODE (type) =3D=3D REAL_TYPE && TYPE_PRECISION (type) =3D=3D = 16) > return "DF16_"; > > + /* Mangle all vector type for vector extension. */ > + /* The mangle name follows the rule of RVV LLVM > + that is "u" + length of (abi_name) + abi_name. */ > + if (TYPE_NAME (type) !=3D NULL) > + { > + const char *res =3D riscv_vector::mangle_builtin_type (type); > + if (res) > + return res; > + } > + > /* Use the default mangling. */ > return NULL; > } > @@ -6290,6 +6336,44 @@ riscv_reinit (void) > #define TARGET_RUN_TARGET_SELFTESTS selftest::riscv_run_selftests > #endif /* #if CHECKING_P */ > > +/* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */ > + > +static bool > +riscv_vector_mode_supported_p (machine_mode mode) > +{ > + if (TARGET_VECTOR) > + return riscv_v_ext_enabled_vector_mode_p (mode); > + > + return false; > +} > + > +/* Implement TARGET_VERIFY_TYPE_CONTEXT. */ > + > +static bool > +riscv_verify_type_context (location_t loc, type_context_kind context, > + const_tree type, bool silent_p) > +{ > + return riscv_vector::verify_type_context (loc, context, type, silent_p= ); > +} > + > +/* Implement TARGET_VECTOR_ALIGNMENT. */ > + > +static HOST_WIDE_INT > +riscv_vector_alignment (const_tree type) > +{ > + /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can > + be set for non-predicate vectors of booleans. Modes are the most > + direct way we have of identifying real RVV predicate types. */ > + /* FIXME: RVV didn't mention the alignment of bool, we uses > + one byte align. */ > + if (GET_MODE_CLASS (TYPE_MODE (type)) =3D=3D MODE_VECTOR_BOOL) > + return 8; > + > + widest_int min_size > + =3D constant_lower_bound (wi::to_poly_widest (TYPE_SIZE (type))); > + return wi::umin (min_size, 128).to_uhwi (); > +} > + > /* Initialize the GCC target structure. */ > #undef TARGET_ASM_ALIGNED_HI_OP > #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" > @@ -6502,6 +6586,15 @@ riscv_reinit (void) > #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN) > #endif > > +#undef TARGET_VECTOR_MODE_SUPPORTED_P > +#define TARGET_VECTOR_MODE_SUPPORTED_P riscv_vector_mode_supported_p > + > +#undef TARGET_VERIFY_TYPE_CONTEXT > +#define TARGET_VERIFY_TYPE_CONTEXT riscv_verify_type_context > + > +#undef TARGET_VECTOR_ALIGNMENT > +#define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment > + > struct gcc_target targetm =3D TARGET_INITIALIZER; > > #include "gt-riscv.h" > diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv > index 2b82e5f2399..ad9be094ebe 100644 > --- a/gcc/config/riscv/t-riscv > +++ b/gcc/config/riscv/t-riscv > @@ -5,6 +5,16 @@ riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.= cc $(CONFIG_H) \ > $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ > $(srcdir)/config/riscv/riscv-builtins.cc > > +riscv-vector-builtins.o: $(srcdir)/config/riscv/riscv-vector-builtins.cc= \ > + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) $(TM_P_= H) \ > + memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) $(DIAGNOSTIC_H) $(EXPR_= H) \ > + $(FUNCTION_H) fold-const.h gimplify.h explow.h stor-layout.h $(REGS_H)= \ > + alias.h langhooks.h attribs.h stringpool.h $(REGS_H) \ > + $(srcdir)/config/riscv/riscv-vector-builtins.h \ > + $(srcdir)/config/riscv/riscv-vector-builtins.def > + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ > + $(srcdir)/config/riscv/riscv-vector-builtins.cc > + > riscv-sr.o: $(srcdir)/config/riscv/riscv-sr.cc $(CONFIG_H) \ > $(SYSTEM_H) $(TM_H) > $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/abi-1.c > new file mode 100644 > index 00000000000..5acfbbe3f87 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c > @@ -0,0 +1,63 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=3Drv*v*= " } } */ > + > +void foo0 () {__rvv_bool64_t t;} > +void foo1 () {__rvv_bool32_t t;} > +void foo2 () {__rvv_bool16_t t;} > +void foo3 () {__rvv_bool8_t t;} > +void foo4 () {__rvv_bool4_t t;} > +void foo5 () {__rvv_bool2_t t;} > +void foo6 () {__rvv_bool1_t t;} > +void foo7 () {__rvv_int8mf8_t t;} > +void foo8 () {__rvv_uint8mf8_t t;} > +void foo9 () {__rvv_int8mf4_t t;} > +void foo10 () {__rvv_uint8mf4_t t;} > +void foo11 () {__rvv_int8mf2_t t;} > +void foo12 () {__rvv_uint8mf2_t t;} > +void foo13 () {__rvv_int8m1_t t;} > +void foo14 () {__rvv_uint8m1_t t;} > +void foo15 () {__rvv_int8m2_t t;} > +void foo16 () {__rvv_uint8m2_t t;} > +void foo17 () {__rvv_int8m4_t t;} > +void foo18 () {__rvv_uint8m4_t t;} > +void foo19 () {__rvv_int8m8_t t;} > +void foo20 () {__rvv_uint8m8_t t;} > +void foo21 () {__rvv_int16mf4_t t;} > +void foo22 () {__rvv_uint16mf4_t t;} > +void foo23 () {__rvv_int16mf2_t t;} > +void foo24 () {__rvv_uint16mf2_t t;} > +void foo25 () {__rvv_int16m1_t t;} > +void foo26 () {__rvv_uint16m1_t t;} > +void foo27 () {__rvv_int16m2_t t;} > +void foo28 () {__rvv_uint16m2_t t;} > +void foo29 () {__rvv_int16m4_t t;} > +void foo30 () {__rvv_uint16m4_t t;} > +void foo31 () {__rvv_int16m8_t t;} > +void foo32 () {__rvv_uint16m8_t t;} > +void foo33 () {__rvv_int32mf2_t t;} > +void foo34 () {__rvv_uint32mf2_t t;} > +void foo35 () {__rvv_int32m1_t t;} > +void foo36 () {__rvv_uint32m1_t t;} > +void foo37 () {__rvv_int32m2_t t;} > +void foo38 () {__rvv_uint32m2_t t;} > +void foo39 () {__rvv_int32m4_t t;} > +void foo40 () {__rvv_uint32m4_t t;} > +void foo41 () {__rvv_int32m8_t t;} > +void foo42 () {__rvv_uint32m8_t t;} > +void foo43 () {__rvv_int64m1_t t;} > +void foo44 () {__rvv_uint64m1_t t;} > +void foo45 () {__rvv_int64m2_t t;} > +void foo46 () {__rvv_uint64m2_t t;} > +void foo47 () {__rvv_int64m4_t t;} > +void foo48 () {__rvv_uint64m4_t t;} > +void foo49 () {__rvv_int64m8_t t;} > +void foo50 () {__rvv_uint64m8_t t;} > +void foo57 () {__rvv_float32mf2_t t;} > +void foo58 () {__rvv_float32m1_t t;} > +void foo59 () {__rvv_float32m2_t t;} > +void foo60 () {__rvv_float32m4_t t;} > +void foo61 () {__rvv_float32m8_t t;} > +void foo62 () {__rvv_float64m1_t t;} > +void foo63 () {__rvv_float64m2_t t;} > +void foo64 () {__rvv_float64m4_t t;} > +void foo65 () {__rvv_float64m8_t t;} > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/abi-2.c > new file mode 100644 > index 00000000000..a09e0c28206 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c > @@ -0,0 +1,63 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv32gc -mabi=3Dilp32d" } */ > + > +void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv= _bool64_t'} } */ > +void foo1 () {__rvv_bool32_t t;} /* { dg-error {unknown type name '__rvv= _bool32_t'} } */ > +void foo2 () {__rvv_bool16_t t;} /* { dg-error {unknown type name '__rvv= _bool16_t'} } */ > +void foo3 () {__rvv_bool8_t t;} /* { dg-error {unknown type name '__rvv_= bool8_t'} } */ > +void foo4 () {__rvv_bool4_t t;} /* { dg-error {unknown type name '__rvv_= bool4_t'} } */ > +void foo5 () {__rvv_bool2_t t;} /* { dg-error {unknown type name '__rvv_= bool2_t'} } */ > +void foo6 () {__rvv_bool1_t t;} /* { dg-error {unknown type name '__rvv_= bool1_t'} } */ > +void foo7 () {__rvv_int8mf8_t t;} /* { dg-error {unknown type name '__rv= v_int8mf8_t'} } */ > +void foo8 () {__rvv_uint8mf8_t t;} /* { dg-error {unknown type name '__r= vv_uint8mf8_t'} } */ > +void foo9 () {__rvv_int8mf4_t t;} /* { dg-error {unknown type name '__rv= v_int8mf4_t'} } */ > +void foo10 () {__rvv_uint8mf4_t t;} /* { dg-error {unknown type name '__= rvv_uint8mf4_t'} } */ > +void foo11 () {__rvv_int8mf2_t t;} /* { dg-error {unknown type name '__r= vv_int8mf2_t'} } */ > +void foo12 () {__rvv_uint8mf2_t t;} /* { dg-error {unknown type name '__= rvv_uint8mf2_t'} } */ > +void foo13 () {__rvv_int8m1_t t;} /* { dg-error {unknown type name '__rv= v_int8m1_t'} } */ > +void foo14 () {__rvv_uint8m1_t t;} /* { dg-error {unknown type name '__r= vv_uint8m1_t'} } */ > +void foo15 () {__rvv_int8m2_t t;} /* { dg-error {unknown type name '__rv= v_int8m2_t'} } */ > +void foo16 () {__rvv_uint8m2_t t;} /* { dg-error {unknown type name '__r= vv_uint8m2_t'} } */ > +void foo17 () {__rvv_int8m4_t t;} /* { dg-error {unknown type name '__rv= v_int8m4_t'} } */ > +void foo18 () {__rvv_uint8m4_t t;} /* { dg-error {unknown type name '__r= vv_uint8m4_t'} } */ > +void foo19 () {__rvv_int8m8_t t;} /* { dg-error {unknown type name '__rv= v_int8m8_t'} } */ > +void foo20 () {__rvv_uint8m8_t t;} /* { dg-error {unknown type name '__r= vv_uint8m8_t'} } */ > +void foo21 () {__rvv_int16mf4_t t;} /* { dg-error {unknown type name '__= rvv_int16mf4_t'} } */ > +void foo22 () {__rvv_uint16mf4_t t;} /* { dg-error {unknown type name '_= _rvv_uint16mf4_t'} } */ > +void foo23 () {__rvv_int16mf2_t t;} /* { dg-error {unknown type name '__= rvv_int16mf2_t'} } */ > +void foo24 () {__rvv_uint16mf2_t t;} /* { dg-error {unknown type name '_= _rvv_uint16mf2_t'} } */ > +void foo25 () {__rvv_int16m1_t t;} /* { dg-error {unknown type name '__r= vv_int16m1_t'} } */ > +void foo26 () {__rvv_uint16m1_t t;} /* { dg-error {unknown type name '__= rvv_uint16m1_t'} } */ > +void foo27 () {__rvv_int16m2_t t;} /* { dg-error {unknown type name '__r= vv_int16m2_t'} } */ > +void foo28 () {__rvv_uint16m2_t t;} /* { dg-error {unknown type name '__= rvv_uint16m2_t'} } */ > +void foo29 () {__rvv_int16m4_t t;} /* { dg-error {unknown type name '__r= vv_int16m4_t'} } */ > +void foo30 () {__rvv_uint16m4_t t;} /* { dg-error {unknown type name '__= rvv_uint16m4_t'} } */ > +void foo31 () {__rvv_int16m8_t t;} /* { dg-error {unknown type name '__r= vv_int16m8_t'} } */ > +void foo32 () {__rvv_uint16m8_t t;} /* { dg-error {unknown type name '__= rvv_uint16m8_t'} } */ > +void foo33 () {__rvv_int32mf2_t t;} /* { dg-error {unknown type name '__= rvv_int32mf2_t'} } */ > +void foo34 () {__rvv_uint32mf2_t t;} /* { dg-error {unknown type name '_= _rvv_uint32mf2_t'} } */ > +void foo35 () {__rvv_int32m1_t t;} /* { dg-error {unknown type name '__r= vv_int32m1_t'} } */ > +void foo36 () {__rvv_uint32m1_t t;} /* { dg-error {unknown type name '__= rvv_uint32m1_t'} } */ > +void foo37 () {__rvv_int32m2_t t;} /* { dg-error {unknown type name '__r= vv_int32m2_t'} } */ > +void foo38 () {__rvv_uint32m2_t t;} /* { dg-error {unknown type name '__= rvv_uint32m2_t'} } */ > +void foo39 () {__rvv_int32m4_t t;} /* { dg-error {unknown type name '__r= vv_int32m4_t'} } */ > +void foo40 () {__rvv_uint32m4_t t;} /* { dg-error {unknown type name '__= rvv_uint32m4_t'} } */ > +void foo41 () {__rvv_int32m8_t t;} /* { dg-error {unknown type name '__r= vv_int32m8_t'} } */ > +void foo42 () {__rvv_uint32m8_t t;} /* { dg-error {unknown type name '__= rvv_uint32m8_t'} } */ > +void foo43 () {__rvv_int64m1_t t;} /* { dg-error {unknown type name '__r= vv_int64m1_t'} } */ > +void foo44 () {__rvv_uint64m1_t t;} /* { dg-error {unknown type name '__= rvv_uint64m1_t'} } */ > +void foo45 () {__rvv_int64m2_t t;} /* { dg-error {unknown type name '__r= vv_int64m2_t'} } */ > +void foo46 () {__rvv_uint64m2_t t;} /* { dg-error {unknown type name '__= rvv_uint64m2_t'} } */ > +void foo47 () {__rvv_int64m4_t t;} /* { dg-error {unknown type name '__r= vv_int64m4_t'} } */ > +void foo48 () {__rvv_uint64m4_t t;} /* { dg-error {unknown type name '__= rvv_uint64m4_t'} } */ > +void foo49 () {__rvv_int64m8_t t;} /* { dg-error {unknown type name '__r= vv_int64m8_t'} } */ > +void foo50 () {__rvv_uint64m8_t t;} /* { dg-error {unknown type name '__= rvv_uint64m8_t'} } */ > +void foo57 () {__rvv_float32mf2_t t;} /* { dg-error {unknown type name '= __rvv_float32mf2_t'} } */ > +void foo58 () {__rvv_float32m1_t t;} /* { dg-error {unknown type name '_= _rvv_float32m1_t'} } */ > +void foo59 () {__rvv_float32m2_t t;} /* { dg-error {unknown type name '_= _rvv_float32m2_t'} } */ > +void foo60 () {__rvv_float32m4_t t;} /* { dg-error {unknown type name '_= _rvv_float32m4_t'} } */ > +void foo61 () {__rvv_float32m8_t t;} /* { dg-error {unknown type name '_= _rvv_float32m8_t'} } */ > +void foo62 () {__rvv_float64m1_t t;} /* { dg-error {unknown type name '_= _rvv_float64m1_t'} } */ > +void foo63 () {__rvv_float64m2_t t;} /* { dg-error {unknown type name '_= _rvv_float64m2_t'} } */ > +void foo64 () {__rvv_float64m4_t t;} /* { dg-error {unknown type name '_= _rvv_float64m4_t'} } */ > +void foo65 () {__rvv_float64m8_t t;} /* { dg-error {unknown type name '_= _rvv_float64m8_t'} } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/abi-3.c > new file mode 100644 > index 00000000000..aa92ecd170b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c > @@ -0,0 +1,63 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv32gc_zve64x -mabi=3Dilp32d" } */ > + > +void foo0 () {__rvv_bool64_t t;} > +void foo1 () {__rvv_bool32_t t;} > +void foo2 () {__rvv_bool16_t t;} > +void foo3 () {__rvv_bool8_t t;} > +void foo4 () {__rvv_bool4_t t;} > +void foo5 () {__rvv_bool2_t t;} > +void foo6 () {__rvv_bool1_t t;} > +void foo7 () {__rvv_int8mf8_t t;} > +void foo8 () {__rvv_uint8mf8_t t;} > +void foo9 () {__rvv_int8mf4_t t;} > +void foo10 () {__rvv_uint8mf4_t t;} > +void foo11 () {__rvv_int8mf2_t t;} > +void foo12 () {__rvv_uint8mf2_t t;} > +void foo13 () {__rvv_int8m1_t t;} > +void foo14 () {__rvv_uint8m1_t t;} > +void foo15 () {__rvv_int8m2_t t;} > +void foo16 () {__rvv_uint8m2_t t;} > +void foo17 () {__rvv_int8m4_t t;} > +void foo18 () {__rvv_uint8m4_t t;} > +void foo19 () {__rvv_int8m8_t t;} > +void foo20 () {__rvv_uint8m8_t t;} > +void foo21 () {__rvv_int16mf4_t t;} > +void foo22 () {__rvv_uint16mf4_t t;} > +void foo23 () {__rvv_int16mf2_t t;} > +void foo24 () {__rvv_uint16mf2_t t;} > +void foo25 () {__rvv_int16m1_t t;} > +void foo26 () {__rvv_uint16m1_t t;} > +void foo27 () {__rvv_int16m2_t t;} > +void foo28 () {__rvv_uint16m2_t t;} > +void foo29 () {__rvv_int16m4_t t;} > +void foo30 () {__rvv_uint16m4_t t;} > +void foo31 () {__rvv_int16m8_t t;} > +void foo32 () {__rvv_uint16m8_t t;} > +void foo33 () {__rvv_int32mf2_t t;} > +void foo34 () {__rvv_uint32mf2_t t;} > +void foo35 () {__rvv_int32m1_t t;} > +void foo36 () {__rvv_uint32m1_t t;} > +void foo37 () {__rvv_int32m2_t t;} > +void foo38 () {__rvv_uint32m2_t t;} > +void foo39 () {__rvv_int32m4_t t;} > +void foo40 () {__rvv_uint32m4_t t;} > +void foo41 () {__rvv_int32m8_t t;} > +void foo42 () {__rvv_uint32m8_t t;} > +void foo43 () {__rvv_int64m1_t t;} > +void foo44 () {__rvv_uint64m1_t t;} > +void foo45 () {__rvv_int64m2_t t;} > +void foo46 () {__rvv_uint64m2_t t;} > +void foo47 () {__rvv_int64m4_t t;} > +void foo48 () {__rvv_uint64m4_t t;} > +void foo49 () {__rvv_int64m8_t t;} > +void foo50 () {__rvv_uint64m8_t t;} > +void foo57 () {__rvv_float32mf2_t t;} /* { dg-error {unknown type name '= __rvv_float32mf2_t'} } */ > +void foo58 () {__rvv_float32m1_t t;} /* { dg-error {unknown type name '_= _rvv_float32m1_t'} } */ > +void foo59 () {__rvv_float32m2_t t;} /* { dg-error {unknown type name '_= _rvv_float32m2_t'} } */ > +void foo60 () {__rvv_float32m4_t t;} /* { dg-error {unknown type name '_= _rvv_float32m4_t'} } */ > +void foo61 () {__rvv_float32m8_t t;} /* { dg-error {unknown type name '_= _rvv_float32m8_t'} } */ > +void foo62 () {__rvv_float64m1_t t;} /* { dg-error {unknown type name '_= _rvv_float64m1_t'} } */ > +void foo63 () {__rvv_float64m2_t t;} /* { dg-error {unknown type name '_= _rvv_float64m2_t'} } */ > +void foo64 () {__rvv_float64m4_t t;} /* { dg-error {unknown type name '_= _rvv_float64m4_t'} } */ > +void foo65 () {__rvv_float64m8_t t;} /* { dg-error {unknown type name '_= _rvv_float64m8_t'} } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/abi-4.c > new file mode 100644 > index 00000000000..9d5cfe564c5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c > @@ -0,0 +1,63 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv32gc_zve64f -mabi=3Dilp32d" } */ > + > +void foo0 () {__rvv_bool64_t t;} > +void foo1 () {__rvv_bool32_t t;} > +void foo2 () {__rvv_bool16_t t;} > +void foo3 () {__rvv_bool8_t t;} > +void foo4 () {__rvv_bool4_t t;} > +void foo5 () {__rvv_bool2_t t;} > +void foo6 () {__rvv_bool1_t t;} > +void foo7 () {__rvv_int8mf8_t t;} > +void foo8 () {__rvv_uint8mf8_t t;} > +void foo9 () {__rvv_int8mf4_t t;} > +void foo10 () {__rvv_uint8mf4_t t;} > +void foo11 () {__rvv_int8mf2_t t;} > +void foo12 () {__rvv_uint8mf2_t t;} > +void foo13 () {__rvv_int8m1_t t;} > +void foo14 () {__rvv_uint8m1_t t;} > +void foo15 () {__rvv_int8m2_t t;} > +void foo16 () {__rvv_uint8m2_t t;} > +void foo17 () {__rvv_int8m4_t t;} > +void foo18 () {__rvv_uint8m4_t t;} > +void foo19 () {__rvv_int8m8_t t;} > +void foo20 () {__rvv_uint8m8_t t;} > +void foo21 () {__rvv_int16mf4_t t;} > +void foo22 () {__rvv_uint16mf4_t t;} > +void foo23 () {__rvv_int16mf2_t t;} > +void foo24 () {__rvv_uint16mf2_t t;} > +void foo25 () {__rvv_int16m1_t t;} > +void foo26 () {__rvv_uint16m1_t t;} > +void foo27 () {__rvv_int16m2_t t;} > +void foo28 () {__rvv_uint16m2_t t;} > +void foo29 () {__rvv_int16m4_t t;} > +void foo30 () {__rvv_uint16m4_t t;} > +void foo31 () {__rvv_int16m8_t t;} > +void foo32 () {__rvv_uint16m8_t t;} > +void foo33 () {__rvv_int32mf2_t t;} > +void foo34 () {__rvv_uint32mf2_t t;} > +void foo35 () {__rvv_int32m1_t t;} > +void foo36 () {__rvv_uint32m1_t t;} > +void foo37 () {__rvv_int32m2_t t;} > +void foo38 () {__rvv_uint32m2_t t;} > +void foo39 () {__rvv_int32m4_t t;} > +void foo40 () {__rvv_uint32m4_t t;} > +void foo41 () {__rvv_int32m8_t t;} > +void foo42 () {__rvv_uint32m8_t t;} > +void foo43 () {__rvv_int64m1_t t;} > +void foo44 () {__rvv_uint64m1_t t;} > +void foo45 () {__rvv_int64m2_t t;} > +void foo46 () {__rvv_uint64m2_t t;} > +void foo47 () {__rvv_int64m4_t t;} > +void foo48 () {__rvv_uint64m4_t t;} > +void foo49 () {__rvv_int64m8_t t;} > +void foo50 () {__rvv_uint64m8_t t;} > +void foo57 () {__rvv_float32mf2_t t;} > +void foo58 () {__rvv_float32m1_t t;} > +void foo59 () {__rvv_float32m2_t t;} > +void foo60 () {__rvv_float32m4_t t;} > +void foo61 () {__rvv_float32m8_t t;} > +void foo62 () {__rvv_float64m1_t t;} /* { dg-error {unknown type name '_= _rvv_float64m1_t'} } */ > +void foo63 () {__rvv_float64m2_t t;} /* { dg-error {unknown type name '_= _rvv_float64m2_t'} } */ > +void foo64 () {__rvv_float64m4_t t;} /* { dg-error {unknown type name '_= _rvv_float64m4_t'} } */ > +void foo65 () {__rvv_float64m8_t t;} /* { dg-error {unknown type name '_= _rvv_float64m8_t'} } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/abi-5.c > new file mode 100644 > index 00000000000..63095960147 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c > @@ -0,0 +1,63 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv32gc_zve64d -mabi=3Dilp32d" } */ > + > +void foo0 () {__rvv_bool64_t t;} > +void foo1 () {__rvv_bool32_t t;} > +void foo2 () {__rvv_bool16_t t;} > +void foo3 () {__rvv_bool8_t t;} > +void foo4 () {__rvv_bool4_t t;} > +void foo5 () {__rvv_bool2_t t;} > +void foo6 () {__rvv_bool1_t t;} > +void foo7 () {__rvv_int8mf8_t t;} > +void foo8 () {__rvv_uint8mf8_t t;} > +void foo9 () {__rvv_int8mf4_t t;} > +void foo10 () {__rvv_uint8mf4_t t;} > +void foo11 () {__rvv_int8mf2_t t;} > +void foo12 () {__rvv_uint8mf2_t t;} > +void foo13 () {__rvv_int8m1_t t;} > +void foo14 () {__rvv_uint8m1_t t;} > +void foo15 () {__rvv_int8m2_t t;} > +void foo16 () {__rvv_uint8m2_t t;} > +void foo17 () {__rvv_int8m4_t t;} > +void foo18 () {__rvv_uint8m4_t t;} > +void foo19 () {__rvv_int8m8_t t;} > +void foo20 () {__rvv_uint8m8_t t;} > +void foo21 () {__rvv_int16mf4_t t;} > +void foo22 () {__rvv_uint16mf4_t t;} > +void foo23 () {__rvv_int16mf2_t t;} > +void foo24 () {__rvv_uint16mf2_t t;} > +void foo25 () {__rvv_int16m1_t t;} > +void foo26 () {__rvv_uint16m1_t t;} > +void foo27 () {__rvv_int16m2_t t;} > +void foo28 () {__rvv_uint16m2_t t;} > +void foo29 () {__rvv_int16m4_t t;} > +void foo30 () {__rvv_uint16m4_t t;} > +void foo31 () {__rvv_int16m8_t t;} > +void foo32 () {__rvv_uint16m8_t t;} > +void foo33 () {__rvv_int32mf2_t t;} > +void foo34 () {__rvv_uint32mf2_t t;} > +void foo35 () {__rvv_int32m1_t t;} > +void foo36 () {__rvv_uint32m1_t t;} > +void foo37 () {__rvv_int32m2_t t;} > +void foo38 () {__rvv_uint32m2_t t;} > +void foo39 () {__rvv_int32m4_t t;} > +void foo40 () {__rvv_uint32m4_t t;} > +void foo41 () {__rvv_int32m8_t t;} > +void foo42 () {__rvv_uint32m8_t t;} > +void foo43 () {__rvv_int64m1_t t;} > +void foo44 () {__rvv_uint64m1_t t;} > +void foo45 () {__rvv_int64m2_t t;} > +void foo46 () {__rvv_uint64m2_t t;} > +void foo47 () {__rvv_int64m4_t t;} > +void foo48 () {__rvv_uint64m4_t t;} > +void foo49 () {__rvv_int64m8_t t;} > +void foo50 () {__rvv_uint64m8_t t;} > +void foo57 () {__rvv_float32mf2_t t;} > +void foo58 () {__rvv_float32m1_t t;} > +void foo59 () {__rvv_float32m2_t t;} > +void foo60 () {__rvv_float32m4_t t;} > +void foo61 () {__rvv_float32m8_t t;} > +void foo62 () {__rvv_float64m1_t t;} > +void foo63 () {__rvv_float64m2_t t;} > +void foo64 () {__rvv_float64m4_t t;} > +void foo65 () {__rvv_float64m8_t t;} > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/abi-6.c > new file mode 100644 > index 00000000000..0d31a0ca891 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c > @@ -0,0 +1,63 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv32gc_zve32x -mabi=3Dilp32d" } */ > + > +void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv= _bool64_t'} } */ > +void foo1 () {__rvv_bool32_t t;} > +void foo2 () {__rvv_bool16_t t;} > +void foo3 () {__rvv_bool8_t t;} > +void foo4 () {__rvv_bool4_t t;} > +void foo5 () {__rvv_bool2_t t;} > +void foo6 () {__rvv_bool1_t t;} > +void foo7 () {__rvv_int8mf8_t t;} /* { dg-error {unknown type name '__rv= v_int8mf8_t'} } */ > +void foo8 () {__rvv_uint8mf8_t t;} /* { dg-error {unknown type name '__r= vv_uint8mf8_t'} } */ > +void foo9 () {__rvv_int8mf4_t t;} > +void foo10 () {__rvv_uint8mf4_t t;} > +void foo11 () {__rvv_int8mf2_t t;} > +void foo12 () {__rvv_uint8mf2_t t;} > +void foo13 () {__rvv_int8m1_t t;} > +void foo14 () {__rvv_uint8m1_t t;} > +void foo15 () {__rvv_int8m2_t t;} > +void foo16 () {__rvv_uint8m2_t t;} > +void foo17 () {__rvv_int8m4_t t;} > +void foo18 () {__rvv_uint8m4_t t;} > +void foo19 () {__rvv_int8m8_t t;} > +void foo20 () {__rvv_uint8m8_t t;} > +void foo21 () {__rvv_int16mf4_t t;} /* { dg-error {unknown type name '__= rvv_int16mf4_t'} } */ > +void foo22 () {__rvv_uint16mf4_t t;} /* { dg-error {unknown type name '_= _rvv_uint16mf4_t'} } */ > +void foo23 () {__rvv_int16mf2_t t;} > +void foo24 () {__rvv_uint16mf2_t t;} > +void foo25 () {__rvv_int16m1_t t;} > +void foo26 () {__rvv_uint16m1_t t;} > +void foo27 () {__rvv_int16m2_t t;} > +void foo28 () {__rvv_uint16m2_t t;} > +void foo29 () {__rvv_int16m4_t t;} > +void foo30 () {__rvv_uint16m4_t t;} > +void foo31 () {__rvv_int16m8_t t;} > +void foo32 () {__rvv_uint16m8_t t;} > +void foo33 () {__rvv_int32mf2_t t;} /* { dg-error {unknown type name '__= rvv_int32mf2_t'} } */ > +void foo34 () {__rvv_uint32mf2_t t;} /* { dg-error {unknown type name '_= _rvv_uint32mf2_t'} } */ > +void foo35 () {__rvv_int32m1_t t;} > +void foo36 () {__rvv_uint32m1_t t;} > +void foo37 () {__rvv_int32m2_t t;} > +void foo38 () {__rvv_uint32m2_t t;} > +void foo39 () {__rvv_int32m4_t t;} > +void foo40 () {__rvv_uint32m4_t t;} > +void foo41 () {__rvv_int32m8_t t;} > +void foo42 () {__rvv_uint32m8_t t;} > +void foo43 () {__rvv_int64m1_t t;} /* { dg-error {unknown type name '__r= vv_int64m1_t'} } */ > +void foo44 () {__rvv_uint64m1_t t;} /* { dg-error {unknown type name '__= rvv_uint64m1_t'} } */ > +void foo45 () {__rvv_int64m2_t t;} /* { dg-error {unknown type name '__r= vv_int64m2_t'} } */ > +void foo46 () {__rvv_uint64m2_t t;} /* { dg-error {unknown type name '__= rvv_uint64m2_t'} } */ > +void foo47 () {__rvv_int64m4_t t;} /* { dg-error {unknown type name '__r= vv_int64m4_t'} } */ > +void foo48 () {__rvv_uint64m4_t t;} /* { dg-error {unknown type name '__= rvv_uint64m4_t'} } */ > +void foo49 () {__rvv_int64m8_t t;} /* { dg-error {unknown type name '__r= vv_int64m8_t'} } */ > +void foo50 () {__rvv_uint64m8_t t;} /* { dg-error {unknown type name '__= rvv_uint64m8_t'} } */ > +void foo57 () {__rvv_float32mf2_t t;} /* { dg-error {unknown type name '= __rvv_float32mf2_t'} } */ > +void foo58 () {__rvv_float32m1_t t;} /* { dg-error {unknown type name '_= _rvv_float32m1_t'} } */ > +void foo59 () {__rvv_float32m2_t t;} /* { dg-error {unknown type name '_= _rvv_float32m2_t'} } */ > +void foo60 () {__rvv_float32m4_t t;} /* { dg-error {unknown type name '_= _rvv_float32m4_t'} } */ > +void foo61 () {__rvv_float32m8_t t;} /* { dg-error {unknown type name '_= _rvv_float32m8_t'} } */ > +void foo62 () {__rvv_float64m1_t t;} /* { dg-error {unknown type name '_= _rvv_float64m1_t'} } */ > +void foo63 () {__rvv_float64m2_t t;} /* { dg-error {unknown type name '_= _rvv_float64m2_t'} } */ > +void foo64 () {__rvv_float64m4_t t;} /* { dg-error {unknown type name '_= _rvv_float64m4_t'} } */ > +void foo65 () {__rvv_float64m8_t t;} /* { dg-error {unknown type name '_= _rvv_float64m8_t'} } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/abi-7.c > new file mode 100644 > index 00000000000..49f404e1a7c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c > @@ -0,0 +1,63 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv32gc_zve32f -mabi=3Dilp32d" } */ > + > +void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv= _bool64_t'} } */ > +void foo1 () {__rvv_bool32_t t;} > +void foo2 () {__rvv_bool16_t t;} > +void foo3 () {__rvv_bool8_t t;} > +void foo4 () {__rvv_bool4_t t;} > +void foo5 () {__rvv_bool2_t t;} > +void foo6 () {__rvv_bool1_t t;} > +void foo7 () {__rvv_int8mf8_t t;} /* { dg-error {unknown type name '__rv= v_int8mf8_t'} } */ > +void foo8 () {__rvv_uint8mf8_t t;} /* { dg-error {unknown type name '__r= vv_uint8mf8_t'} } */ > +void foo9 () {__rvv_int8mf4_t t;} > +void foo10 () {__rvv_uint8mf4_t t;} > +void foo11 () {__rvv_int8mf2_t t;} > +void foo12 () {__rvv_uint8mf2_t t;} > +void foo13 () {__rvv_int8m1_t t;} > +void foo14 () {__rvv_uint8m1_t t;} > +void foo15 () {__rvv_int8m2_t t;} > +void foo16 () {__rvv_uint8m2_t t;} > +void foo17 () {__rvv_int8m4_t t;} > +void foo18 () {__rvv_uint8m4_t t;} > +void foo19 () {__rvv_int8m8_t t;} > +void foo20 () {__rvv_uint8m8_t t;} > +void foo21 () {__rvv_int16mf4_t t;} /* { dg-error {unknown type name '__= rvv_int16mf4_t'} } */ > +void foo22 () {__rvv_uint16mf4_t t;} /* { dg-error {unknown type name '_= _rvv_uint16mf4_t'} } */ > +void foo23 () {__rvv_int16mf2_t t;} > +void foo24 () {__rvv_uint16mf2_t t;} > +void foo25 () {__rvv_int16m1_t t;} > +void foo26 () {__rvv_uint16m1_t t;} > +void foo27 () {__rvv_int16m2_t t;} > +void foo28 () {__rvv_uint16m2_t t;} > +void foo29 () {__rvv_int16m4_t t;} > +void foo30 () {__rvv_uint16m4_t t;} > +void foo31 () {__rvv_int16m8_t t;} > +void foo32 () {__rvv_uint16m8_t t;} > +void foo33 () {__rvv_int32mf2_t t;} /* { dg-error {unknown type name '__= rvv_int32mf2_t'} } */ > +void foo34 () {__rvv_uint32mf2_t t;} /* { dg-error {unknown type name '_= _rvv_uint32mf2_t'} } */ > +void foo35 () {__rvv_int32m1_t t;} > +void foo36 () {__rvv_uint32m1_t t;} > +void foo37 () {__rvv_int32m2_t t;} > +void foo38 () {__rvv_uint32m2_t t;} > +void foo39 () {__rvv_int32m4_t t;} > +void foo40 () {__rvv_uint32m4_t t;} > +void foo41 () {__rvv_int32m8_t t;} > +void foo42 () {__rvv_uint32m8_t t;} > +void foo43 () {__rvv_int64m1_t t;} /* { dg-error {unknown type name '__r= vv_int64m1_t'} } */ > +void foo44 () {__rvv_uint64m1_t t;} /* { dg-error {unknown type name '__= rvv_uint64m1_t'} } */ > +void foo45 () {__rvv_int64m2_t t;} /* { dg-error {unknown type name '__r= vv_int64m2_t'} } */ > +void foo46 () {__rvv_uint64m2_t t;} /* { dg-error {unknown type name '__= rvv_uint64m2_t'} } */ > +void foo47 () {__rvv_int64m4_t t;} /* { dg-error {unknown type name '__r= vv_int64m4_t'} } */ > +void foo48 () {__rvv_uint64m4_t t;} /* { dg-error {unknown type name '__= rvv_uint64m4_t'} } */ > +void foo49 () {__rvv_int64m8_t t;} /* { dg-error {unknown type name '__r= vv_int64m8_t'} } */ > +void foo50 () {__rvv_uint64m8_t t;} /* { dg-error {unknown type name '__= rvv_uint64m8_t'} } */ > +void foo57 () {__rvv_float32mf2_t t;} /* { dg-error {unknown type name '= __rvv_float32mf2_t'} } */ > +void foo58 () {__rvv_float32m1_t t;} > +void foo59 () {__rvv_float32m2_t t;} > +void foo60 () {__rvv_float32m4_t t;} > +void foo61 () {__rvv_float32m8_t t;} > +void foo62 () {__rvv_float64m1_t t;} /* { dg-error {unknown type name '_= _rvv_float64m1_t'} } */ > +void foo63 () {__rvv_float64m2_t t;} /* { dg-error {unknown type name '_= _rvv_float64m2_t'} } */ > +void foo64 () {__rvv_float64m4_t t;} /* { dg-error {unknown type name '_= _rvv_float64m4_t'} } */ > +void foo65 () {__rvv_float64m8_t t;} /* { dg-error {unknown type name '_= _rvv_float64m8_t'} } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/g= cc.target/riscv/rvv/rvv.exp > new file mode 100644 > index 00000000000..33304809285 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > @@ -0,0 +1,47 @@ > +# Copyright (C) 2022-2022 Free Software Foundation, Inc. > + > +# This program is free software; you can redistribute it and/or modify > +# it under the terms of the GNU General Public License as published by > +# the Free Software Foundation; either version 3 of the License, or > +# (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with GCC; see the file COPYING3. If not see > +# . > + > +# GCC testsuite that uses the `dg.exp' driver. > + > +# Exit immediately if this isn't a RISC-V target. > +if ![istarget riscv*-*-*] then { > + return > +} > + > +# Load support procs. > +load_lib gcc-dg.exp > + > +# If a testcase doesn't have special options, use these. > +global DEFAULT_CFLAGS > +if ![info exists DEFAULT_CFLAGS] then { > + set DEFAULT_CFLAGS " -ansi -pedantic-errors" > +} > + > +set gcc_march "rv64gcv_zfh" > +if [istarget riscv32-*-*] then { > + set gcc_march "rv32gcv_zfh" > +} > + > +# Initialize `dg'. > +dg-init > + > +# Main loop. > +set CFLAGS "$DEFAULT_CFLAGS -march=3D$gcc_march -O3" > +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ > + "" $CFLAGS > + > +# All done. > +dg-finish > \ No newline at end of file > -- > 2.36.1 >