From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa2c.google.com (mail-vk1-xa2c.google.com [IPv6:2607:f8b0:4864:20::a2c]) by sourceware.org (Postfix) with ESMTPS id CD8053858C2A for ; Thu, 17 Aug 2023 03:32:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CD8053858C2A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa2c.google.com with SMTP id 71dfb90a1353d-4881c30b1b3so934596e0c.1 for ; Wed, 16 Aug 2023 20:32:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692243154; x=1692847954; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=gp1YqXtBfHlIP3O58JK345O7GLmPHqQ2rf0BtgK3uEw=; b=nLiL0BNsjdcYrG1kCvfKqUwFk6GhHuK9lIeKYIwAju7odAW/Avb/lFhPSuKXQ2aRMJ OE4RVznaPxKbJF7vIlZ9KasUNUITQU6Dhaa4TAAYmnDvVdu6fvUQvXE+WlxzK1IpUXbx dzwWF3BkklrjIgESEKtigggf/sXlc0gsPEUwILsGteMc8Vs00voIB72fVdCyvXP26f+a qCZR6o7dWpuR9JkuwI8rophT2XB1H3ZLKo+UvCXE7WKhGcBcZPS8nVI3IoqiFLIRn5m5 T3vf1fKQDswizhSPYgh6e9rkdAI9oFq1ZrpN30hCy8uHCOda5Ld7O4bNBGzwLD1XeI1o X9UQ== X-Google-DKIM-Signature: v=1; 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boundary="00000000000010088706031610e1" X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000010088706031610e1 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lgtm Pan Li via Gcc-patches =E6=96=BC 2023=E5=B9=B48=E6= =9C=8817=E6=97=A5 =E9=80=B1=E5=9B=9B=EF=BC=8C10:19=E5=AF=AB=E9=81=93=EF=BC= =9A > From: Pan Li > > This patch would like to support the rounding mode API for the > VFNCVT.F.{X|XU|F}.W as the below samples. > > * __riscv_vfncvt_f_x_w_f32m1_rm > * __riscv_vfncvt_f_x_w_f32m1_rm_m > * __riscv_vfncvt_f_xu_w_f32m1_rm > * __riscv_vfncvt_f_xu_w_f32m1_rm_m > * __riscv_vfncvt_f_f_w_f32m1_rm > * __riscv_vfncvt_f_f_w_f32m1_rm_m > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-bases.cc > (class vfncvt_f): Add frm_op_type template arg. > (vfncvt_f_frm_obj): New declaration. > (BASE): Ditto. > * config/riscv/riscv-vector-builtins-bases.h: Ditto. > * config/riscv/riscv-vector-builtins-functions.def > (vfncvt_f_frm): New intrinsic function def. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-ncvt-f.c: New test. > --- > .../riscv/riscv-vector-builtins-bases.cc | 10 ++- > .../riscv/riscv-vector-builtins-bases.h | 1 + > .../riscv/riscv-vector-builtins-functions.def | 3 + > .../riscv/rvv/base/float-point-ncvt-f.c | 69 +++++++++++++++++++ > 4 files changed, 82 insertions(+), 1 deletion(-) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c > > diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc > b/gcc/config/riscv/riscv-vector-builtins-bases.cc > index acadec2afca..ad04647f9ba 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc > +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc > @@ -1786,9 +1786,15 @@ public: > } > }; > > +template > class vfncvt_f : public function_base > { > public: > + bool has_rounding_mode_operand_p () const override > + { > + return FRM_OP =3D=3D HAS_FRM; > + } > + > rtx expand (function_expander &e) const override > { > if (e.op_info->op =3D=3D OP_TYPE_f_w) > @@ -2512,7 +2518,8 @@ static CONSTEXPR const > vfncvt_x vfncvt_xu_obj; > static CONSTEXPR const vfncvt_x > vfncvt_xu_frm_obj; > static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj; > static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj; > -static CONSTEXPR const vfncvt_f vfncvt_f_obj; > +static CONSTEXPR const vfncvt_f vfncvt_f_obj; > +static CONSTEXPR const vfncvt_f vfncvt_f_frm_obj; > static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj; > static CONSTEXPR const reducop vredsum_obj; > static CONSTEXPR const reducop vredmaxu_obj; > @@ -2769,6 +2776,7 @@ BASE (vfncvt_xu_frm) > BASE (vfncvt_rtz_x) > BASE (vfncvt_rtz_xu) > BASE (vfncvt_f) > +BASE (vfncvt_f_frm) > BASE (vfncvt_rod_f) > BASE (vredsum) > BASE (vredmaxu) > diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h > b/gcc/config/riscv/riscv-vector-builtins-bases.h > index 9bd09a41960..c8c649c4bb0 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-bases.h > +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h > @@ -226,6 +226,7 @@ extern const function_base *const vfncvt_xu_frm; > extern const function_base *const vfncvt_rtz_x; > extern const function_base *const vfncvt_rtz_xu; > extern const function_base *const vfncvt_f; > +extern const function_base *const vfncvt_f_frm; > extern const function_base *const vfncvt_rod_f; > extern const function_base *const vredsum; > extern const function_base *const vredmaxu; > diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def > b/gcc/config/riscv/riscv-vector-builtins-functions.def > index 1e0e989fc2a..cfbc125dcd8 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-functions.def > +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def > @@ -474,6 +474,9 @@ DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, > full_preds, f_to_nf_f_w_ops) > > DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, > f_to_ni_f_w_ops) > DEF_RVV_FUNCTION (vfncvt_xu_frm, narrow_alu_frm, full_preds, > f_to_nu_f_w_ops) > +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, > i_to_nf_x_w_ops) > +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, > u_to_nf_xu_w_ops) > +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, > f_to_nf_f_w_ops) > > /* 14. Vector Reduction Operations. */ > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c > new file mode 100644 > index 00000000000..d6d4be5e98e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c > @@ -0,0 +1,69 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3 -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vfloat32m1_t > +test_riscv_vfncvt_f_x_w_f32m1_rm (vint64m2_t op1, size_t vl) { > + return __riscv_vfncvt_f_x_w_f32m1_rm (op1, 0, vl); > +} > + > +vfloat32m1_t > +test_vfncvt_f_x_w_f32m1_rm_m (vbool32_t mask, vint64m2_t op1, size_t vl)= { > + return __riscv_vfncvt_f_x_w_f32m1_rm_m (mask, op1, 1, vl); > +} > + > +vfloat32m1_t > +test_riscv_vfncvt_f_xu_w_f32m1_rm (vuint64m2_t op1, size_t vl) { > + return __riscv_vfncvt_f_xu_w_f32m1_rm (op1, 0, vl); > +} > + > +vfloat32m1_t > +test_vfncvt_f_xu_w_f32m1_rm_m (vbool32_t mask, vuint64m2_t op1, size_t > vl) { > + return __riscv_vfncvt_f_xu_w_f32m1_rm_m (mask, op1, 1, vl); > +} > + > +vfloat32m1_t > +test_riscv_vfncvt_f_f_w_f32m1_rm (vfloat64m2_t op1, size_t vl) { > + return __riscv_vfncvt_f_f_w_f32m1_rm (op1, 0, vl); > +} > + > +vfloat32m1_t > +test_vfncvt_f_f_w_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, size_t > vl) { > + return __riscv_vfncvt_f_f_w_f32m1_rm_m (mask, op1, 1, vl); > +} > + > +vfloat32m1_t > +test_riscv_vfncvt_f_x_w_f32m1 (vint64m2_t op1, size_t vl) { > + return __riscv_vfncvt_f_x_w_f32m1 (op1, vl); > +} > + > +vfloat32m1_t > +test_vfncvt_f_x_w_f32m1_m (vbool32_t mask, vint64m2_t op1, size_t vl) { > + return __riscv_vfncvt_f_x_w_f32m1_m (mask, op1, vl); > +} > + > +vfloat32m1_t > +test_riscv_vfncvt_f_xu_w_f32m1 (vuint64m2_t op1, size_t vl) { > + return __riscv_vfncvt_f_xu_w_f32m1 (op1, vl); > +} > + > +vfloat32m1_t > +test_vfncvt_f_xu_w_f32m1_m (vbool32_t mask, vuint64m2_t op1, size_t vl) { > + return __riscv_vfncvt_f_xu_w_f32m1_m (mask, op1, vl); > +} > + > +vfloat32m1_t > +test_riscv_vfncvt_f_f_w_f32m1 (vfloat64m2_t op1, size_t vl) { > + return __riscv_vfncvt_f_f_w_f32m1 (op1, vl); > +} > + > +vfloat32m1_t > +test_vfncvt_f_f_w_f32m1_m (vbool32_t mask, vfloat64m2_t op1, size_t vl) { > + return __riscv_vfncvt_f_f_w_f32m1_m (mask, op1, vl); > +} > + > +/* { dg-final { scan-assembler-times > {vfncvt\.f\.[xuf]+\.w\s+v[0-9]+,\s*v[0-9]+} 12 } } */ > +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 6 } } */ > +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 6 } } */ > +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 6 } } */ > -- > 2.34.1 > > --00000000000010088706031610e1--