From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id 4D6A7384515B for ; Tue, 5 Dec 2023 15:12:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4D6A7384515B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4D6A7384515B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::634 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701789134; cv=none; b=xSHS4KZZ4c+BVYoZwCtgaUd0k5+9f1hxAcVKScIP3MafKxO7sHDYquFDOgkzaciMmYmGOJeipmnr9CCOEPzBwZuS28oirn2+FmNFR5kZfLjmIU+DJJJbqaa2gPcHSxMggpbvihcy5YXy5jYHOxBkxlUYGMJaIoVeNrgxPnWd2BI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701789134; c=relaxed/simple; bh=x8lG8g+l1b2xWxu581X2vUbHgskov517R7a2vrjedtA=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=iuZWYYtHFoGO+BElP9AI2kR9nj4ikkrwdLqkGhsqDWXi0OuC9HzNCxdcrGzKn8WdhT9k2X6fg+F6d8RKMcExZlY6qhCEWXtUCDAtBdZPKL8vpWOlQsw6kD7UEpKOlH8lM7j1qqzCbJogHOAJSJI/un22QN++JOk2E83SFdBKUTU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-a0029289b1bso744864566b.1 for ; Tue, 05 Dec 2023 07:12:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1701789129; x=1702393929; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=ApX+aM3x06M9UuZrSzdp/ZKB14fNJIyQ9hzMIfdDing=; b=YGfZc2ah56SWxv0Phd2CeTrLpY15/2aQF7JW8pXwW3DJtc4M9aeNPPl5Zlznmjc2QF 4MhMkNWGX1TKO5Ei2lj2bBC3Yjzivj2soyaQhBINUmQdPVsOa79cmYAwu0qYaxeZiAy0 Ua2/es6Qw7nYbFM909+AfA/DBov5hXDG2fnuRDS7k1MbLflwo/B8Tei7QZeYMnK8k9Xn 4zjmrX78AE0Hp2z2CnTyai6uh8MYtPrAtBSTgEtVdni8yHuNyUoB8jnPMDRwOtg2fPxK NDsMINGXWzcaqOc07g/xuG6uPgMPXWppLN3iT440jvym8g0d2Sh4z+uJSzG7PRYbNvLL yMEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701789129; x=1702393929; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ApX+aM3x06M9UuZrSzdp/ZKB14fNJIyQ9hzMIfdDing=; b=vXeDuCutmfWVjouiKfwq+e2j05dnVGkVu6FJ7fsga7SQZz8yLq2/MOVw/Q+wErrKF3 Qtjm9U3U3W9P7KJ/osnnDKJk98Acc/3GneFBuANAqNgwzv/NhlPT7eHBR4onK1zK6I9Z EQ05vfWfErmHAllG8RCg1p/m5voB62bEwTNAUeH1Vq0dP40H7lkQ1w/O4N+1wobvmMy7 C7hl+3xWvIZePn0PCmjNGYAKCpcaFL6fmX1J2suqg1vX8h2Fsr0hmQdsyfFb2CsO7O9v QyJa5GwD66QnvfoWu02nhi3mjpTrno1FBx4gm8/ISX2bWxxkEDobYRiSJWL6N8zUm0va YNgw== X-Gm-Message-State: AOJu0Yx4f5+bht8WEwipalEhgPiZDPYBBmc/eKMoRBS8BW3k+VH722DY E53erx2OVtzu0BKJaJ3xC1BTJDWlbJCTkLcyN7ze7kvJyOw= X-Google-Smtp-Source: AGHT+IF51WKRVsKdxxV+aNR1GPz8OTOYLBATqF5HuEEdKqhmX4DRkSbrOgsjUOWq8+eIFMfGohbfvRi7z75ukEJsysM= X-Received: by 2002:a17:906:5185:b0:a19:a1ba:8ce5 with SMTP id y5-20020a170906518500b00a19a1ba8ce5mr3823353ejk.131.1701789128509; Tue, 05 Dec 2023 07:12:08 -0800 (PST) MIME-Version: 1.0 References: <20231113133530.1727444-1-mary.bennett@embecosm.com> <20231128131615.3986922-1-mary.bennett@embecosm.com> <20231128131615.3986922-3-mary.bennett@embecosm.com> In-Reply-To: <20231128131615.3986922-3-mary.bennett@embecosm.com> From: Kito Cheng Date: Tue, 5 Dec 2023 23:11:56 +0800 Message-ID: Subject: Re: [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors To: Mary Bennett Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Tue, Nov 28, 2023 at 9:17=E2=80=AFPM Mary Bennett wrote: > > gcc/ChangeLog: > * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. > * config/riscv/corev.md: Likewise. > --- > gcc/config/riscv/constraints.md | 15 ++++++++------- > gcc/config/riscv/corev.md | 4 ++-- > 2 files changed, 10 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constrain= ts.md > index 68be4515c04..2711efe68c5 100644 > --- a/gcc/config/riscv/constraints.md > +++ b/gcc/config/riscv/constraints.md > @@ -151,13 +151,6 @@ > (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? G= R_REGS : NO_REGS" > "An integer register for ZFA or XTheadFmv.") > > -;; CORE-V Constraints > -(define_constraint "CVP2" > - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2" > - (and (match_code "const_int") > - (and (match_test "IN_RANGE (ival, 0, 1073741823)") > - (match_test "exact_log2 (ival + 1) !=3D -1")))) > - > ;; Vector constraints. > > (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" > @@ -246,3 +239,11 @@ > A MEM with a valid address for th.[l|s]*ur* instructions." > (and (match_code "mem") > (match_test "th_memidx_legitimate_index_p (op, true)"))) > + > +;; CORE-V Constraints > +(define_constraint "CV_alu_pow2" > + "@internal > + Checking for CORE-V ALU clip if ival plus 1 is a power of 2" > + (and (match_code "const_int") > + (and (match_test "IN_RANGE (ival, 0, 1073741823)") > + (match_test "exact_log2 (ival + 1) !=3D -1")))) > diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md > index c7a2ba07bcc..92bf0b5d6a6 100644 > --- a/gcc/config/riscv/corev.md > +++ b/gcc/config/riscv/corev.md > @@ -516,7 +516,7 @@ > (define_insn "riscv_cv_alu_clip" > [(set (match_operand:SI 0 "register_operand" "=3Dr,r") > (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") > - (match_operand:SI 2 "immediate_register_operand" "CVP2,r"= )] > + (match_operand:SI 2 "immediate_register_operand" "CV_alu_= pow2,r")] > UNSPEC_CV_ALU_CLIP))] > > "TARGET_XCVALU && !TARGET_64BIT" > @@ -529,7 +529,7 @@ > (define_insn "riscv_cv_alu_clipu" > [(set (match_operand:SI 0 "register_operand" "=3Dr,r") > (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") > - (match_operand:SI 2 "immediate_register_operand" "CVP2,r"= )] > + (match_operand:SI 2 "immediate_register_operand" "CV_alu_= pow2,r")] > UNSPEC_CV_ALU_CLIPU))] > > "TARGET_XCVALU && !TARGET_64BIT" > -- > 2.34.1 >