From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by sourceware.org (Postfix) with ESMTPS id 5663D3836008 for ; Thu, 1 Sep 2022 02:13:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5663D3836008 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x52b.google.com with SMTP id y64so8891829ede.2 for ; Wed, 31 Aug 2022 19:13:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=pdc0ZLiLp/nCOJQQHKr1JKYDs4ucy38QH+OSSuPxZi4=; b=DNKZJYicygNEyYicAwBZ/L6XOaysKClxTnlKVHOl3dZ0IcxvIUuQdi1GWN76EbRvSy yl2wlXdKDSRbM+SPJG5n51oEOKhFwpk4OmvVYz9QfSctCdrLcDHQujYTxjLPG8OLWDq0 T1JSc4M3l8sE2dnoBsqcmwvBqThmW5m62ReHJSDRPdH5atb5/Vu8GpQRuSpomZhFD3VQ jVx7lDbNFYGGmCYG2TaaaUAMdFMh2KMta4uJjkcC5D2ntzwCo2U3HU/nq5UrwYkRM6rM a0Tge+cp/eeFW1nZtd/8OQZIrNynNPwSC1CF7/gPW4MyZhkLdY4/m2ZLpJ9Yz8LcCxKo KBtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=pdc0ZLiLp/nCOJQQHKr1JKYDs4ucy38QH+OSSuPxZi4=; b=HqYfwkGv8GZAdJkTwA2Ks+9FLvkCSObBfNtpSdNM4kU4+qqrkjd9UUN4m2qPuKV1a7 vuaDdYhHYNJ8L8P4ASVJ5+ZwnjEz2A3vcf0/K8BBkzwrsHLDh+JdcT7MiCTDOYlrN0bP 7zw8dVWK3zn4Ftj7kUgZwQZc+sAqXEnsPYYTKfpVVeiSexhXkEtlCpAnU5uaHo0i2Hr1 usE4NSURwKyy4fZh+6hmn4NJFst+Diwj350UuKnFIEUc9EFjKyP3h12blVxUT/Mbhkqj y2XfIpN3AQfrj4Gu6m3AM2ouKE1lPvnlAGDmPkBt+Zb6ZsDptC9GlqGoLUn83hog6avw rr4A== X-Gm-Message-State: ACgBeo1/HFRwNTtkh3LMd3BlSZUgrjGV6h7Qr5zsJ5rDC4ozqHLM9q0Y bDPKof2dMgXxiJIEHK8B87lxce0MRmehXKTzXYA= X-Google-Smtp-Source: AA6agR7/KlB+KWCRHGLNSsoq9pbr7SXK+2afMSgTJuA5XZm1PK5Z+TJxHnoZcIrRp5euTIDvf4c2HhefG2IB18tqHhQ= X-Received: by 2002:a05:6402:1943:b0:443:5ffb:b04e with SMTP id f3-20020a056402194300b004435ffbb04emr2226187edz.230.1661998401783; Wed, 31 Aug 2022 19:13:21 -0700 (PDT) MIME-Version: 1.0 References: <20220830062027.252003-1-juzhe.zhong@rivai.ai> In-Reply-To: <20220830062027.252003-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Thu, 1 Sep 2022 10:13:10 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add csrr vlenb instruction. To: juzhe.zhong@rivai.ai Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed. On Tue, Aug 30, 2022 at 2:21 PM wrote: > > From: zhongjuzhe > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_const_insns): Add cost of poly_int. > (riscv_output_move): Add csrr vlenb assembly. > * config/riscv/riscv.md (move_type): Add csrr vlenb type. > (ext): New attribute. > (ext_enabled): Ditto. > (enabled): Ditto. > > --- > gcc/config/riscv/riscv.cc | 13 +++++++ > gcc/config/riscv/riscv.md | 79 ++++++++++++++++++++++++++++----------- > 2 files changed, 70 insertions(+), 22 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index ef606f33983..50de6a83cba 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -1136,6 +1136,12 @@ riscv_const_insns (rtx x) > case LABEL_REF: > return riscv_symbol_insns (riscv_classify_symbol (x)); > > + /* TODO: In RVV, we get CONST_POLY_INT by using csrr vlenb > + instruction and several scalar shift or mult instructions, > + it is so far unknown. We set it to 4 temporarily. */ > + case CONST_POLY_INT: > + return 4; > + > default: > return 0; > } > @@ -2507,6 +2513,13 @@ riscv_output_move (rtx dest, rtx src) > return "fld\t%0,%1"; > } > } > + if (dest_code == REG && GP_REG_P (REGNO (dest)) && src_code == CONST_POLY_INT) > + { > + /* we only want a single full vector register vlen > + read after reload. */ > + gcc_assert (known_eq (rtx_to_poly_int64 (src), BYTES_PER_RISCV_VECTOR)); > + return "csrr\t%0,vlenb"; > + } > gcc_unreachable (); > } > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 63bb3c8debc..2bfab198370 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -148,7 +148,7 @@ > ;; scheduling type to be "multi" instead. > (define_attr "move_type" > "unknown,load,fpload,store,fpstore,mtc,mfc,move,fmove, > - const,logical,arith,andi,shift_shift" > + const,logical,arith,andi,shift_shift,rdvlenb" > (const_string "unknown")) > > ;; Main data type used by the insn > @@ -166,6 +166,35 @@ > (const_string "yes")] > (const_string "no"))) > > +;; ISA attributes. > +(define_attr "ext" "base,f,d,vector" > + (const_string "base")) > + > +;; True if the extension is enabled. > +(define_attr "ext_enabled" "no,yes" > + (cond [(eq_attr "ext" "base") > + (const_string "yes") > + > + (and (eq_attr "ext" "f") > + (match_test "TARGET_HARD_FLOAT")) > + (const_string "yes") > + > + (and (eq_attr "ext" "d") > + (match_test "TARGET_DOUBLE_FLOAT")) > + (const_string "yes") > + > + (and (eq_attr "ext" "vector") > + (match_test "TARGET_VECTOR")) > + (const_string "yes") > + ] > + (const_string "no"))) > + > +;; Attribute to control enable or disable instructions. > +(define_attr "enabled" "no,yes" > + (cond [(eq_attr "ext_enabled" "no") > + (const_string "no")] > + (const_string "yes"))) > + > ;; Classification of each insn. > ;; branch conditional branch > ;; jump unconditional jump > @@ -326,7 +355,8 @@ > (eq_attr "dword_mode" "yes")) > (const_string "multi") > (eq_attr "move_type" "move") (const_string "move") > - (eq_attr "move_type" "const") (const_string "const")] > + (eq_attr "move_type" "const") (const_string "const") > + (eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")] > (const_string "unknown"))) > > ;; Length of instruction in bytes. > @@ -1633,24 +1663,26 @@ > }) > > (define_insn "*movdi_32bit" > - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m, *f,*f,*r,*f,*m") > - (match_operand:DI 1 "move_operand" " r,i,m,r,*J*r,*m,*f,*f,*f"))] > + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m, *f,*f,*r,*f,*m,r") > + (match_operand:DI 1 "move_operand" " r,i,m,r,*J*r,*m,*f,*f,*f,vp"))] > "!TARGET_64BIT > && (register_operand (operands[0], DImode) > || reg_or_0_operand (operands[1], DImode))" > { return riscv_output_move (operands[0], operands[1]); } > - [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore") > - (set_attr "mode" "DI")]) > + [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") > + (set_attr "mode" "DI") > + (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) > > (define_insn "*movdi_64bit" > - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m") > - (match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f"))] > + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m,r") > + (match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f,vp"))] > "TARGET_64BIT > && (register_operand (operands[0], DImode) > || reg_or_0_operand (operands[1], DImode))" > { return riscv_output_move (operands[0], operands[1]); } > - [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore") > - (set_attr "mode" "DI")]) > + [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") > + (set_attr "mode" "DI") > + (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) > > ;; 32-bit Integer moves > > @@ -1664,13 +1696,14 @@ > }) > > (define_insn "*movsi_internal" > - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*m") > - (match_operand:SI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f"))] > + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*m,r") > + (match_operand:SI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,vp"))] > "(register_operand (operands[0], SImode) > || reg_or_0_operand (operands[1], SImode))" > { return riscv_output_move (operands[0], operands[1]); } > - [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore") > - (set_attr "mode" "SI")]) > + [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb") > + (set_attr "mode" "SI") > + (set_attr "ext" "base,base,base,base,f,f,f,f,vector")]) > > ;; 16-bit Integer moves > > @@ -1689,13 +1722,14 @@ > }) > > (define_insn "*movhi_internal" > - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r") > - (match_operand:HI 1 "move_operand" " r,T,m,rJ,*r*J,*f"))] > + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r") > + (match_operand:HI 1 "move_operand" " r,T,m,rJ,*r*J,*f,vp"))] > "(register_operand (operands[0], HImode) > || reg_or_0_operand (operands[1], HImode))" > { return riscv_output_move (operands[0], operands[1]); } > - [(set_attr "move_type" "move,const,load,store,mtc,mfc") > - (set_attr "mode" "HI")]) > + [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") > + (set_attr "mode" "HI") > + (set_attr "ext" "base,base,base,base,f,f,vector")]) > > ;; HImode constant generation; see riscv_move_integer for details. > ;; si+si->hi without truncation is legal because of > @@ -1731,13 +1765,14 @@ > }) > > (define_insn "*movqi_internal" > - [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r") > - (match_operand:QI 1 "move_operand" " r,I,m,rJ,*r*J,*f"))] > + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r") > + (match_operand:QI 1 "move_operand" " r,I,m,rJ,*r*J,*f,vp"))] > "(register_operand (operands[0], QImode) > || reg_or_0_operand (operands[1], QImode))" > { return riscv_output_move (operands[0], operands[1]); } > - [(set_attr "move_type" "move,const,load,store,mtc,mfc") > - (set_attr "mode" "QI")]) > + [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") > + (set_attr "mode" "QI") > + (set_attr "ext" "base,base,base,base,f,f,vector")]) > > ;; 32-bit floating point moves > > -- > 2.36.1 >