From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by sourceware.org (Postfix) with ESMTPS id 4372F3858D38 for ; Tue, 27 Dec 2022 19:51:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4372F3858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ed1-x52c.google.com with SMTP id m21so20295980edc.3 for ; Tue, 27 Dec 2022 11:51:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=RaRSo9RyZaHoO4EaBrOFfwOR/77K5f1KYfHXBgUzvY4=; b=MXtyeXrFVf+IWf1+/U/6GHU1DbZWXQZTbTb5hOne9+2RUdMxEZgYzfrhBDXdhuwXwe prLDeEJaraG9VKBMqaLp05uInFp71IvTAyBvRkED250qRkmoi2M4aGHc+G0fbr4o+6ay Bol80JwfR59f6P9YFqfhdxkZLsLw5hu2p1ee+2Gg18Q0wLo0cCN9TBMKfcjvMFJmGaF5 bH8feblQO9vd0HiF9erJ8TzRRN5jin1DWvZnJjAs1mohfssJuQ1BHfyQ9KlWRY4GdkJ4 rVJmcc1GHSKDngYCG8L73qRRbQTRSI3s0uk2I8G4udBBaZmGXimTITjFPwNc2oW9zMFN y5fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=RaRSo9RyZaHoO4EaBrOFfwOR/77K5f1KYfHXBgUzvY4=; b=Z+303cXNyoGDncLEcEL6UL++ra75aA/3ntY1j6XSE5+UYdJoEgEozufhkxReohXSWr ceJ42au+kUsGP/nYkh63J+eaIPWoPhi8XXu1r8Kbg8Di8rlEFPV3TiE5lFe6q/Djn0Cb 49vdyicE3O9W2uUfTJarWZElK+OARrSSZj3OxEinLWN1h3ZvqvTm/KsDOFQ8HUT73wfR 5pTTKkOTlHZvr+cT1i9WkTcSuHQZ5Fb0sqaTPOdBrNWqSsGYF5yg8OyJUNKik4ZBGRyL Jp+BuXv8aFBJQzAJB00VRtZGfzStDmRk4CjOrrOMwPl9lGiGmIx3dJFgVwx+Qg9soTbF Cxzw== X-Gm-Message-State: AFqh2kpVC3piYZFOrsWQ2DhJqk2Ut1YLEgf80KURn0JTAYyw2uQhmerZ VV8kQ4HiDe3B3mwwEjbMqwHxsNhzywF/KV3sofxIXA== X-Google-Smtp-Source: AMrXdXtRBOYWl7LCdRtXrBtMqSunpW28M7/6nOMftZpEQd/T/kkKqzZe6Gp98JytUkhrNVxQFwtbL1VmWgFXPRZboTQ= X-Received: by 2002:aa7:c3c1:0:b0:47f:95e:5cea with SMTP id l1-20020aa7c3c1000000b0047f095e5ceamr1390861edr.83.1672170684056; Tue, 27 Dec 2022 11:51:24 -0800 (PST) MIME-Version: 1.0 References: <20221219010838.3878675-1-christoph.muellner@vrull.eu> <20221219010838.3878675-2-christoph.muellner@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Tue, 27 Dec 2022 20:51:13 +0100 Message-ID: Subject: Re: [PATCH v2 01/11] riscv: attr: Synchronize comments with code To: Kito Cheng Cc: Christoph Muellner , gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Jeff Law , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: multipart/alternative; boundary="000000000000a0961e05f0d49368" X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000a0961e05f0d49368 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Applied to master, thanks! Philipp. On Mon, 19 Dec 2022 at 03:49, Kito Cheng wrote: > LGTM, you can commit this separately if you want :) > > On Mon, Dec 19, 2022 at 9:09 AM Christoph Muellner > wrote: > > > > From: Christoph M=C3=BCllner > > > > The comment above the enumeration of existing attributes got out of > > order and a few entries were forgotten. > > This patch synchronizes the comments according to the list. > > This commit does not include any functional change. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv.md: Sync comments with code. > > > > Signed-off-by: Christoph M=C3=BCllner > > --- > > gcc/config/riscv/riscv.md | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > index df57e2b0b4a..a8bb331f25c 100644 > > --- a/gcc/config/riscv/riscv.md > > +++ b/gcc/config/riscv/riscv.md > > @@ -220,7 +220,6 @@ (define_attr "enabled" "no,yes" > > ;; mfc transfer from coprocessor > > ;; const load constant > > ;; arith integer arithmetic instructions > > -;; auipc integer addition to PC > > ;; logical integer logical instructions > > ;; shift integer shift instructions > > ;; slt set less than instructions > > @@ -236,9 +235,13 @@ (define_attr "enabled" "no,yes" > > ;; fcvt floating point convert > > ;; fsqrt floating point square root > > ;; multi multiword sequence (or user asm statements) > > +;; auipc integer addition to PC > > +;; sfb_alu SFB ALU instruction > > ;; nop no operation > > ;; ghost an instruction that produces no real code > > ;; bitmanip bit manipulation instructions > > +;; rotate rotation instructions > > +;; atomic atomic instructions > > ;; Classification of RVV instructions which will be added to each RVV > .md pattern and used by scheduler. > > ;; rdvlenb vector byte length vlenb csrr read > > ;; rdvl vector length vl csrr read > > -- > > 2.38.1 > > > --000000000000a0961e05f0d49368--