From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by sourceware.org (Postfix) with ESMTPS id 4E945385840C for ; Mon, 14 Nov 2022 20:03:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4E945385840C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x229.google.com with SMTP id l8so14711857ljh.13 for ; Mon, 14 Nov 2022 12:03:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=eyoXNNAarHZhR00qHURzMzVcUnZtqCgMguvIcwq9Vks=; b=W/ovyGxKExUTUSWNVGbR6SG/NIzvyNW2FVvn6dyDjSCzNev7gWPS6sRY7mZvlw6WyM Eu5xIhtWc3Cna5SSB1c06v28NNRwUAQLbQDeQhb6PqmlpqL3b4OmMePyhFfLahnPXHtT ILI6ZBXczGd0fcILUBd/DVqcI7YzsyTAlCLY0FHbYIY1YCJdUfSx5OVMr1Q3rsQZ8GCt P71WWQcDXwWN99IMihxswLQ/6WZs7Ii7WyRzCx5xwlHJsiwXjq5dLSVMZSk284zcygWw gXorsVWOBh/hFGTfqJoeI9tHwXuc+I7WJn3mH3y7D6r9pUlug9I1D9PLN38/chTPek2m c6ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=eyoXNNAarHZhR00qHURzMzVcUnZtqCgMguvIcwq9Vks=; b=hY072SZksmbJsNiju6iBF6SyTx9e5OZS+98EJ6Y5mGPBsp1284wGLeYhG11SGrpFwK p0ylmLFIheDX9u+APY2+QvhDKT0FckCX9mVF6F3w8kumdEWgaOuIPlS5AOHl+AMU7if0 At/NCWveKDawuoIohyYkLmbato5UMpEZzWcoVO4NB44c6Y83KvBwxHwe62HBSb3SeezG p9nk1EvpwRwEsdgGIqg+bkDMQ2zp9hxaNQpw24l0K8TPFEe9TBt4R8NXEWP39P6dwj/e 9ud7G5vWmlh8pvFciWNzPfsQWWIK2wmwWPznUFo4urCIiOWMQgIvzKVzKshjJJK58hwb I0SQ== X-Gm-Message-State: ANoB5plydwJtPtx6CsgPz47L/C9ytDY0ydEBv5lb32EeoYxizJMPilx/ jq+rZereDqSiEYTrJXrlESQSHJdZE0npJfPwmey6MA== X-Google-Smtp-Source: AA0mqf6sR+cCnwJ926GWLh4d8cEhPEGK0QGoBKYY+sEm3Ltx6+mhIbCanupdTNkd5musjB2/diiwBfxvbM9jRAyrDs0= X-Received: by 2002:a2e:9b8d:0:b0:276:ffd1:d7c8 with SMTP id z13-20020a2e9b8d000000b00276ffd1d7c8mr4462108lji.176.1668456229789; Mon, 14 Nov 2022 12:03:49 -0800 (PST) MIME-Version: 1.0 References: <20221113204824.4062042-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Mon, 14 Nov 2022 21:03:38 +0100 Message-ID: Subject: Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion To: Palmer Dabbelt Cc: gcc-patches@gcc.gnu.org, Vineet Gupta , jlaw@ventanamicro.com, Kito Cheng , christoph.muellner@vrull.eu Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 14 Nov 2022 at 21:00, Palmer Dabbelt wrote: > > On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.tomsich@vrull.eu wrote: > > > > This series provides support for the Ventana VT1 (a 4-way superscalar > > rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support > > for the supported instruction fusion patterns. > > > > This includes the addition of the fusion-aware scheduling > > infrastructure for RISC-V and implements idiom recognition for the > > fusion patterns supported by VT1. > > > > Note that we don't signal support for XVentanaCondOps at this point, > > as the XVentanaCondOps support is in-flight separately. Changing the > > defaults for VT1 can happen late in the cycle, so no need to link the > > two different changesets. > > > > Changes in v2: > > - Rebased and changed over to .rst-based documentation > > - Updated to catch more fusion cases > > - Signals support for Zifencei > > > > Philipp Tomsich (2): > > RISC-V: Add basic support for the Ventana-VT1 core > > RISC-V: Add instruction fusion (for ventana-vt1) > > > > gcc/config/riscv/riscv-cores.def | 3 + > > gcc/config/riscv/riscv-opts.h | 2 +- > > gcc/config/riscv/riscv.cc | 233 ++++++++++++++++++ > > .../risc-v-options.rst | 5 +- > > 4 files changed, 240 insertions(+), 3 deletions(-) > > I guess we never really properly talked about this on the GCC mailing > lists, but IMO it's fine to start taking code for designs that have been > announced under the assumption that if the hardware doesn't actually > show up according to those timelines that it will be assumed to have > never existed and thus be removed more quickly than usual. > > That said, I can't find anything describing that the VT-1 exists aside > from these patches. Is there anything that describes this design and > when it's expected to be available? I have to defer to Jeff on this one. Philipp.