Re: [PATCH v2] RISC-V: bitmanip: improve constant-loading for (1ULL << 31) in DImode

[Philipp Tomsich <philipp.tomsich@vrull.eu>]

Thanks, applied to trunk!

On Thu, 2 Jun 2022 at 15:17, Kito Cheng <kito.cheng@gmail.com> wrote:
>
> LGTM
>
> On Mon, May 30, 2022 at 5:52 AM Philipp Tomsich
> <philipp.tomsich@vrull.eu> wrote:
> >
> > The SINGLE_BIT_MASK_OPERAND() is overly restrictive, triggering for
> > bits above 31 only (to side-step any issues with the negative SImode
> > value 0x80000000/(-1ull << 31)/(1 << 31)).  This moves the special
> > handling of this SImode value (i.e. the check for (-1ull << 31) to
> > riscv.cc and relaxes the SINGLE_BIT_MASK_OPERAND() test.
> >
> > With this, the code-generation for loading (1ULL << 31) from:
> >         li      a0,1
> >         slli    a0,a0,31
> > to:
> >         bseti   a0,zero,31
> >
> > gcc/ChangeLog:
> >
> >         * config/riscv/riscv.cc (riscv_build_integer_1): Rewrite value as
> >         (-1 << 31) for the single-bit case, when operating on (1 << 31)
> >         in SImode.
> >         * gcc/config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): Allow for
> >         any single-bit value, moving the special case for (1 << 31) to
> >         riscv_build_integer_1 (in riscv.c).
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> >
> > ---
> >
> > Changes in v2:
> > - Use HOST_WIDE_INT_1U/HOST_WIDE_INT_M1U instead of constants.
> > - Fix some typos in the comment above the rewrite of the value.
> > - Update the comment to clarify that we expect a LUI to be emitted for
> >   the SImode case (i.e. sign-extended for RV64) of (1 << 31).
> >
> >  gcc/config/riscv/riscv.cc |  9 +++++++++
> >  gcc/config/riscv/riscv.h  | 11 ++++-------
> >  2 files changed, 13 insertions(+), 7 deletions(-)
> >
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index f83dc796d88..2e83ca07394 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -420,6 +420,15 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
> >        /* Simply BSETI.  */
> >        codes[0].code = UNKNOWN;
> >        codes[0].value = value;
> > +
> > +      /* RISC-V sign-extends all 32bit values that live in a 32bit
> > +        register.  To avoid paradoxes, we thus need to use the
> > +        sign-extended (negative) representation (-1 << 31) for the
> > +        value, if we want to build (1 << 31) in SImode.  This will
> > +        then expand to an LUI instruction.  */
> > +      if (mode == SImode && value == (HOST_WIDE_INT_1U << 31))
> > +       codes[0].value = (HOST_WIDE_INT_M1U << 31);
> > +
> >        return 1;
> >      }
> >
> > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> > index 5083a1c24b0..6f7f4d3fbdc 100644
> > --- a/gcc/config/riscv/riscv.h
> > +++ b/gcc/config/riscv/riscv.h
> > @@ -528,13 +528,10 @@ enum reg_class
> >    (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)      \
> >     || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
> >
> > -/* If this is a single bit mask, then we can load it with bseti.  But this
> > -   is not useful for any of the low 31 bits because we can use addi or lui
> > -   to load them.  It is wrong for loading SImode 0x80000000 on rv64 because it
> > -   needs to be sign-extended.  So we restrict this to the upper 32-bits
> > -   only.  */
> > -#define SINGLE_BIT_MASK_OPERAND(VALUE) \
> > -  (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32))
> > +/* If this is a single bit mask, then we can load it with bseti.  Special
> > +   handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
> > +#define SINGLE_BIT_MASK_OPERAND(VALUE)                                 \
> > +  (pow2p_hwi (VALUE))
> >
> >  /* Stack layout; function entry, exit and calling.  */
> >
> > --
> > 2.34.1
> >