From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb2f.google.com (mail-yb1-xb2f.google.com [IPv6:2607:f8b0:4864:20::b2f]) by sourceware.org (Postfix) with ESMTPS id 23D363871020 for ; Thu, 6 Oct 2022 09:16:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 23D363871020 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-yb1-xb2f.google.com with SMTP id 126so1537075ybw.3 for ; Thu, 06 Oct 2022 02:16:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date; bh=D8iDsPpJw5zo1YNwbAeybhHSBBEkkd+etJD4pu9hOeA=; b=N889cjs5oM/l9dA7NDRnbh6baCjOygdGEq2uLanNDALP701i0QFYa3nFL6kUQhfIMi 3XkIkAbt5u+dvO1wBKPNbMHyRUOJ8uZWZLtPTYwQygGEk8hwhCCtU2stb/vXvnq8iQas +CC3szaMV6YKp/5ASsZUhWOMWksQqur5z2ftgZsF6PWktrNIIdbiaK9FhiH6M8h+wfRO 5Fukekmu/czH7HCrTJR6tBN3I6W6FIQ5opJnsLSfu2ZSMZHY136H885E3vfD5nD8Ywsh rI9+36dvIbkbkZEFbOCEDh2EW/de5bryEya5hqKhKpEdDXbKNceQIUSftFnL1hByzUuC U3cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date; bh=D8iDsPpJw5zo1YNwbAeybhHSBBEkkd+etJD4pu9hOeA=; b=pHitnzje7vpTS6kZiyyoecMpIRMabV0v0hXUtjwAdictMgssXSWBkfqCrl2OQHzJ/0 gE8XdKD1lVbrKZv5i7M9EnK9p8oc47SG2ztSI2PakS6ZF1Z6XMbYBf0TSWO7SQQo5bRN c2iWpbPLXDEBl5ZxVylBSeMhAY/ag2Ox6klZF3KxRA1q8BwxmDNPvuxciZuZY6FshVmO S1LkK+nPIA2BNoEgecle+ozsFF37tfVoDZBpgg89rPRO2hTktwtnJyzl1F2CXyXPdwBZ Fo4PN8zi73H8fEymN7vUkMA0PtL1V45g0z5lGh9JGmjOAT6OazMTSPubnYe/zWikpj9M R2uQ== X-Gm-Message-State: ACrzQf2If3kcxwx63SKIY7gLYo+G/ntw56VPQtAbOxKTM/bEzumvaAb6 BT3R6c7MIT8VmP1huw60zO945HtCaDzVQ3Va7Td+IA== X-Google-Smtp-Source: AMsMyM4yQmZ29f3tsXrACVvOcllMauh4MRmS96HWSjzY5xwevEm4618CGE6mjKgz0TS4Qv8dDvqGieLUT/T2tvjzfRg= X-Received: by 2002:a25:e7d5:0:b0:6be:8d99:b293 with SMTP id e204-20020a25e7d5000000b006be8d99b293mr3901278ybh.434.1665047787375; Thu, 06 Oct 2022 02:16:27 -0700 (PDT) MIME-Version: 1.0 References: <20221003212402.3337669-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Thu, 6 Oct 2022 11:16:16 +0200 Message-ID: Subject: Re: [PATCH] aarch64: update Ampere-1 core definition To: Philipp Tomsich , gcc-patches@gcc.gnu.org, Tamar Christina , Christoph Muellner , richard.sandiford@arm.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 4 Oct 2022 at 18:43, Richard Sandiford wrote: > > Philipp Tomsich writes: > > This brings the extensions detected by -mcpu=native on Ampere-1 systems > > in sync with the defaults generated for -mcpu=ampere1. > > > > Note that some kernel versions may misreport the presence of PAUTH and > > PREDRES (i.e., -mcpu=native will add 'nopauth' and 'nopredres'). > > > > gcc/ChangeLog: > > > > * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update > > Ampere-1 core entry. > > > > Signed-off-by: Philipp Tomsich > > > > --- > > Ok for backport? > > > > gcc/config/aarch64/aarch64-cores.def | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def > > index 60299160bb6..9090f80b4b7 100644 > > --- a/gcc/config/aarch64/aarch64-cores.def > > +++ b/gcc/config/aarch64/aarch64-cores.def > > @@ -69,7 +69,7 @@ AARCH64_CORE("thunderxt81", thunderxt81, thunderx, V8A, (CRC, CRYPTO), thu > > AARCH64_CORE("thunderxt83", thunderxt83, thunderx, V8A, (CRC, CRYPTO), thunderx, 0x43, 0x0a3, -1) > > > > /* Ampere Computing ('\xC0') cores. */ > > -AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (), ampere1, 0xC0, 0xac3, -1) > > +AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RCPC, RNG, AES, SHA3), ampere1, 0xC0, 0xac3, -1) > > The fact that you had include RCPC here shows that there was a bug > in the definition of Armv8.3-A. I've just pushed a fix for that. > > Otherwise, this seems to line up with the LLVM definition, except > that this definition enables RNG/AEK_RAND whereas the LLVM one doesn't > seem to. Which one's right (or is it me that's wrong)? I just rechecked, and the latest documents (in correspondence to the /proc/cpuinfo-output) confirm that FEAT_RNG is implemented. LLVM needs to be updated to reflect that RNG is implemented. > > Thanks, > Richard > > > > /* Do not swap around "emag" and "xgene1", > > this order is required to handle variant correctly. */ > > AARCH64_CORE("emag", emag, xgene1, V8A, (CRC, CRYPTO), emag, 0x50, 0x000, 3)